From: sashiko-bot@kernel.org
To: "David Heidelberg via B4 Relay" <devnull+david.ixit.cz@kernel.org>
Cc: linux-media@vger.kernel.org
Subject: Re: [PATCH v7 2/8] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes
Date: Fri, 05 Jun 2026 13:30:34 +0000 [thread overview]
Message-ID: <20260605133035.1273F1F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260605-qcom-cphy-v7-2-426c37e9008f@ixit.cz>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Commit message claims to return failure but code does not implement error propagation.
--
commit da5484f83dd0e6203bd1f47a4299fe8d0bb8c433
Author: David Heidelberg <david@ixit.cz>
media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes
This commit adds support for C-PHY lane configuration by utilizing odd
bits instead of the even bits used for D-PHY mode. It updates the lane
mask calculation and enablement routines for C-PHY hardware requirements.
> Since there can be unrecognized configuration allow returning failure.
[Severity: Medium]
The commit message explicitly states "allow returning failure" for
unrecognized configurations, but does the code actually implement this?
Looking at csiphy_get_lane_mask() and csiphy_lanes_enable(), the code does
not appear to propagate any errors. Could the commit message be updated
to reflect the use of warnings, or should the functions be changed to return
an error code?
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index dac8d2ecf7995..fa24fc9706748 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
[ ... ]
> @@ -1113,13 +1114,22 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
>
> static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
> {
> - u8 lane_mask;
> - int i;
> + u8 lane_mask = 0;
> + u8 offset = 0;
>
> - lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> + switch (lane_cfg->phy_cfg) {
> + case V4L2_MBUS_CSI2_CPHY:
> + offset = 1;
> + break;
> + case V4L2_MBUS_CSI2_DPHY:
> + lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> + break;
> + default:
> + break;
> + }
[Severity: Medium]
In csiphy_get_lane_mask(), the default case silently falls through and
returns 0. Is this intended to be treated as a failure condition?
[ ... ]
> @@ -1160,9 +1170,22 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
[ ... ]
> - val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> - for (i = 0; i < c->num_data; i++)
> - val |= BIT(c->data[i].pos * 2);
> + val = 0;
> +
> + switch (c->phy_cfg) {
> + case V4L2_MBUS_CSI2_CPHY:
> + for (i = 0; i < c->num_data; i++)
> + val |= BIT((c->data[i].pos * 2) + 1);
> + break;
> + case V4L2_MBUS_CSI2_DPHY:
> + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> +
> + for (i = 0; i < c->num_data; i++)
> + val |= BIT(c->data[i].pos * 2);
> + break;
> + default:
> + WARN_ONCE(1, "Unsupported bus type %d!\n", c->phy_cfg);
> + }
[Severity: Medium]
Similarly, since csiphy_lanes_enable() has a void return type, the caller
has no way to detect this failure. While misconfiguration might be
prevented earlier during device tree parsing, does this function need to be
updated to actually return the failure mentioned in the commit message?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260605-qcom-cphy-v7-0-426c37e9008f@ixit.cz?part=2
next prev parent reply other threads:[~2026-06-05 13:30 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-05 13:14 [PATCH v7 0/8] media: camss: Add support for C-PHY configuration on Qualcomm platforms David Heidelberg via B4 Relay
2026-06-05 13:14 ` David Heidelberg
2026-06-05 13:14 ` [PATCH v7 1/8] media: qcom: camss: csiphy: Introduce PHY configuration David Heidelberg via B4 Relay
2026-06-05 13:14 ` David Heidelberg
2026-06-05 13:14 ` [PATCH v7 2/8] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes David Heidelberg via B4 Relay
2026-06-05 13:14 ` David Heidelberg
2026-06-05 13:30 ` sashiko-bot [this message]
2026-06-08 18:16 ` Frank Li
2026-06-08 19:32 ` David Heidelberg
2026-06-05 13:14 ` [PATCH v7 3/8] media: qcom: camss: Prepare CSID for C-PHY support David Heidelberg via B4 Relay
2026-06-05 13:14 ` David Heidelberg
2026-06-05 13:35 ` sashiko-bot
2026-06-08 18:18 ` Frank Li
2026-06-05 13:14 ` [PATCH v7 4/8] media: qcom: camss: Initialize lanes after lane configuration is available David Heidelberg via B4 Relay
2026-06-05 13:14 ` David Heidelberg
2026-06-05 13:40 ` sashiko-bot
2026-06-05 13:14 ` [PATCH v7 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init David Heidelberg via B4 Relay
2026-06-05 13:14 ` David Heidelberg
2026-06-08 9:00 ` Bryan O'Donoghue
2026-06-08 10:37 ` David Heidelberg
2026-06-05 13:14 ` [PATCH v7 6/8] media: qcom: camss: csiphy-3ph: Update " David Heidelberg via B4 Relay
2026-06-05 13:14 ` David Heidelberg
2026-06-05 13:14 ` [PATCH v7 7/8] media: qcom: camss: Account for C-PHY when calculating link frequency David Heidelberg via B4 Relay
2026-06-05 13:14 ` David Heidelberg
2026-06-05 14:00 ` sashiko-bot
2026-06-05 13:14 ` [PATCH v7 8/8] media: qcom: camss: Enable C-PHY where available David Heidelberg via B4 Relay
2026-06-05 13:14 ` David Heidelberg
2026-06-08 8:56 ` [PATCH v7 0/8] media: camss: Add support for C-PHY configuration on Qualcomm platforms Bryan O'Donoghue
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