[PATCH 12/12] drm/xe/memirq: Enable compute walker post-sync interrupt

[Stuart Summers <stuart.summers@intel.com>]

Commit 2ddedd4b7b7c ("drm/xe/memirq: Enable GT_MI_USER_INTERRUPT only")
narrowed the MEMIRQ enable mask to GT_MI_USER_INTERRUPT only. Add
the interrupt enable bit for the compute walker post sync interrupt
as well to allow those to go through.

Additionally, the compute walker post sync interrupt vector offset
in the LRC register is currently incorrect. Fix that here.

Bspec: 62346, 72547

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/regs/xe_lrc_layout.h |  3 +++
 drivers/gpu/drm/xe/xe_lrc.c             | 15 ++++++++++++++-
 drivers/gpu/drm/xe/xe_memirq.c          | 12 +++++++++---
 3 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
index 4ab86fc369fd..3c0babaa7902 100644
--- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
+++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
@@ -31,6 +31,9 @@
 #define CTX_INT_SRC_REPORT_REG		(CTX_LRI_INT_REPORT_PTR + 3)
 #define CTX_INT_SRC_REPORT_PTR		(CTX_LRI_INT_REPORT_PTR + 4)
 
+#define CTX_CS_INT_VEC_USER_MASK	REG_GENMASK(9, 0)
+#define CTX_CS_INT_VEC_COMPUTE_MASK	REG_GENMASK(19, 10)
+
 #define CTX_CS_INT_VEC_REG		0x5a
 #define CTX_CS_INT_VEC_DATA		(CTX_CS_INT_VEC_REG + 1)
 
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index a4292a11391d..d6677980be2d 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1527,11 +1527,24 @@ static int xe_lrc_ctx_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, struct
 		xe_lrc_set_ppgtt(lrc, vm);
 
 	if (xe_device_has_msix(xe)) {
+		/*
+		 * Each exec queue is only assigned one MSI-X vector, however
+		 * the LRC allows for different vectors for MI_USER_INT and
+		 * compute walker post sync interrupts. For now, just use the
+		 * same vector for each of the vector types.
+		 */
+		u32 lrc_msix_vec =
+			REG_FIELD_PREP(CTX_CS_INT_VEC_USER_MASK, msix_vec);
+
+		if (GRAPHICS_VERx100(xe) >= 3511)
+			lrc_msix_vec |=
+				REG_FIELD_PREP(CTX_CS_INT_VEC_COMPUTE_MASK, msix_vec);
+
 		xe_lrc_write_ctx_reg(lrc, CTX_INT_STATUS_REPORT_PTR,
 				     xe_memirq_status_ptr(&tile->memirq, hwe));
 		xe_lrc_write_ctx_reg(lrc, CTX_INT_SRC_REPORT_PTR,
 				     xe_memirq_source_ptr(&tile->memirq, hwe));
-		xe_lrc_write_ctx_reg(lrc, CTX_CS_INT_VEC_DATA, msix_vec << 16 | msix_vec);
+		xe_lrc_write_ctx_reg(lrc, CTX_CS_INT_VEC_DATA, lrc_msix_vec);
 	}
 
 	if (xe_gt_has_indirect_ring_state(gt)) {
diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index f94b75eac80f..c00c9f9695d2 100644
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -238,12 +238,18 @@ static int memirq_alloc_pages(struct xe_memirq *memirq)
 
 static void memirq_set_enable(struct xe_memirq *memirq, bool enable)
 {
+	struct xe_device *xe = memirq_to_xe(memirq);
+	u32 int_enables = GT_MI_USER_INTERRUPT;
+
+	if (GRAPHICS_VERx100(xe) >= 3511)
+		int_enables |= GT_COMPUTE_WALKER_INTERRUPT;
+
 	/*
-	 * We only care about the GT_MI_USER_INTERRUPT from the engines and
-	 * the GuC does not look at the ENABLE mask at all.
+	 * Enable MI_USER_INTERRUPT and compute walker post-sync interrupts
+	 * from engines. The GuC does not look at the ENABLE mask at all.
 	 */
 	iosys_map_wr(&memirq->bo->vmap, XE_MEMIRQ_ENABLE_OFFSET, u32,
-		     enable ? GT_MI_USER_INTERRUPT : 0);
+		     enable ? int_enables : 0);
 
 	memirq->enabled = enable;
 }
-- 
2.43.0