[GIT PULL] clk: spacemit: Updates for v7.2

[GIT PULL] clk: spacemit: Updates for v7.2

[Yixun Lan]

From: Yixun Lan <dlan@gentoo.org>

Hi Stephen,

   Please pull SpacemiT's clock changes for v7.2
All clock changes are related to PCIe for K3 SoC.
   Hope this isn't too late..

Yixun Lan

The following changes since commit 254f49634ee16a731174d2ae34bc50bd5f45e731:

  Linux 7.1-rc1 (2026-04-26 14:19:00 -0700)

are available in the Git repository at:

  https://github.com/spacemit-com/linux spacemit-clk-for-7.2-1

for you to fetch changes up to a37c75d7b5bb7f3344b0e639b313ac5ace6244ff:

  clk: spacemit: k3: Add PCIe DBI clock (2026-06-02 07:16:59 +0000)

----------------------------------------------------------------
RISC-V SpacemiT clock changes for 7.2

- Switch parent clock of PCIe
- Fix PCIe clock register offset
- Add PCIe DBI clock

----------------------------------------------------------------
Yixun Lan (4):
      clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
      clk: spacemit: k3: Fix PCIe clock register offset
      dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
      clk: spacemit: k3: Add PCIe DBI clock

 drivers/clk/spacemit/ccu-k3.c                  | 30 +++++++++++++++++---------
 include/dt-bindings/clock/spacemit,k3-clocks.h |  5 +++++
 include/soc/spacemit/k3-syscon.h               |  4 ++--
 3 files changed, 27 insertions(+), 12 deletions(-)

[GIT PULL] clk: spacemit: Updates for v7.2

[Yixun Lan]

From: Yixun Lan <dlan@gentoo.org>

Hi Stephen,

   Please pull SpacemiT's clock changes for v7.2
All clock changes are related to PCIe for K3 SoC.
   Hope this isn't too late..

Yixun Lan

The following changes since commit 254f49634ee16a731174d2ae34bc50bd5f45e731:

  Linux 7.1-rc1 (2026-04-26 14:19:00 -0700)

are available in the Git repository at:

  https://github.com/spacemit-com/linux spacemit-clk-for-7.2-1

for you to fetch changes up to a37c75d7b5bb7f3344b0e639b313ac5ace6244ff:

  clk: spacemit: k3: Add PCIe DBI clock (2026-06-02 07:16:59 +0000)

----------------------------------------------------------------
RISC-V SpacemiT clock changes for 7.2

- Switch parent clock of PCIe
- Fix PCIe clock register offset
- Add PCIe DBI clock

----------------------------------------------------------------
Yixun Lan (4):
      clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
      clk: spacemit: k3: Fix PCIe clock register offset
      dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
      clk: spacemit: k3: Add PCIe DBI clock

 drivers/clk/spacemit/ccu-k3.c                  | 30 +++++++++++++++++---------
 include/dt-bindings/clock/spacemit,k3-clocks.h |  5 +++++
 include/soc/spacemit/k3-syscon.h               |  4 ++--
 3 files changed, 27 insertions(+), 12 deletions(-)

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