Re: [PATCH v6 06/21] dt-bindings: riscv: add Smcntrpmf ISA extension description

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The `smcntrpmf` extension is inserted in the wrong alphabetical order.
- [Low] The description incorrectly refers to `Smcntrpmf` as a 'supervisor-level' extension.
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commit 9fd028f70a33e1a78db2f635eed4200c33b6b90d
Author: Atish Patra <atishp@rivosinc.com>

dt-bindings: riscv: add Smcntrpmf ISA extension description

Add the description for the Smcntrpmf ISA extension.

> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 4be557dc215de..ece3edccee42c 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -189,6 +189,12 @@ properties:
>              mechanism in M-mode as ratified in the 20240326 version of the
>              privileged ISA specification.
>  
> +        - const: smcntrpmf

[Severity: Low]
Is this inserted in the correct alphabetical order?

The multi-letter extensions list in this file explicitly requires entries to be
sorted alphanumerically. Alphabetically, smcntrpmf ("c-n") should come before
the preceding extension (smcsrind, "c-s").

> +          description: |
> +            The standard Smcntrpmf supervisor-level extension for the machine mode

[Severity: Low]
Is "supervisor-level" accurate here?

In the RISC-V ISA naming convention, the "Sm" prefix denotes a standard
machine-level extension, while "Ss" denotes a supervisor-level extension.

Calling it a "supervisor-level extension for the machine mode" seems
contradictory. Could this be a copy-paste error?

> +            to enable privilege mode filtering for cycle and instret counters as
> +            ratified in the 20240326 version of the privileged ISA specification.
> +
>          - const: smmpm
>            description: |
>              The standard Smmpm extension for M-mode pointer masking as

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Sashiko AI review · https://sashiko.dev/#/patchset/20260608-counter_delegation-v6-0-285b72ed65a9@meta.com?part=6