From: sashiko-bot@kernel.org
To: "Atish Patra" <atish.patra@linux.dev>
Cc: devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org,
robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v6 14/21] RISC-V: perf: Skip PMU SBI extension when not implemented
Date: Tue, 09 Jun 2026 06:33:28 +0000 [thread overview]
Message-ID: <20260609063329.66D801F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260608-counter_delegation-v6-14-285b72ed65a9@meta.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
Pre-existing issues:
- [Critical] Missing perf_pmu_unregister() on error paths leads to Use-After-Free of the pmu struct.
- [High] Unconditional cpuhp_state_remove_instance() on an uninitialized hlist_node causes a kernel panic.
--
commit bd51c5655be0902a2fc1fd90b8d692c299e7265b
Author: Charlie Jenkins <charlie@rivosinc.com>
RISC-V: perf: Skip PMU SBI extension when not implemented
When the PMU SBI extension is not implemented, sbi_v2_available should
not be set to true. The SBI implementation for counter config matching
and firmware counter read should also be skipped when the SBI extension
is not implemented.
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 1f16df9d0dd00..5bfcd3821f572 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
[ ... ]
> @@ -2045,12 +2052,13 @@ static int __init rvpmu_devinit(void)
> int ret;
> struct platform_device *pdev;
>
> - if (sbi_spec_version >= sbi_mk_version(0, 3) &&
> - sbi_probe_extension(SBI_EXT_PMU))
> - static_branch_enable(&riscv_pmu_sbi_available);
> + if (sbi_probe_extension(SBI_EXT_PMU)) {
> + if (sbi_spec_version >= sbi_mk_version(0, 3))
> + static_branch_enable(&riscv_pmu_sbi_available);
> + if (sbi_spec_version >= sbi_mk_version(2, 0))
> + sbi_v2_available = true;
> + }
>
> - if (sbi_spec_version >= sbi_mk_version(2, 0))
> - sbi_v2_available = true;
> /*
> * We need all three extensions to be present to access the counters
> * in S-mode via Supervisor Counter delegation.
[Severity: Critical]
This is a pre-existing issue, but I noticed a potential use-after-free in the
error handling path of rvpmu_device_probe() when allocating or registering
fails after perf_pmu_register() succeeds.
If an error occurs, such as pmu_sbi_snapshot_alloc() failing, the code jumps
to out_unregister:
out_unregister:
riscv_pmu_destroy(pmu);
out_free:
kfree(pmu);
return ret;
However, neither the error path nor riscv_pmu_destroy() calls
perf_pmu_unregister(&pmu->pmu).
This leaves the PMU registered in the perf core subsystem while its backing
memory is freed via kfree(). Any subsequent access to the PMU could result
in a use-after-free.
Should perf_pmu_unregister() be called during teardown to avoid memory
corruption?
[Severity: High]
This is a pre-existing issue, but the error teardown path in
rvpmu_device_probe() seems to have a bug that could trigger a kernel panic.
If rvpmu_device_probe() fails before successfully calling
cpuhp_state_add_instance(), it jumps to out_unregister and calls
riscv_pmu_destroy(pmu).
Inside riscv_pmu_destroy(), it unconditionally removes the hotplug instance:
static void riscv_pmu_destroy(struct riscv_pmu *pmu)
{
...
cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
}
Because the pmu struct is allocated with kzalloc() and the node hasn't been
added to the hotplug list yet, its hlist_node is zero-initialized.
When hlist_del() is called internally by cpuhp_state_remove_instance(), it
attempts to dereference node->pprev (which is NULL), causing a NULL pointer
dereference.
Would it be better to check if the node is actually hashed before attempting
to remove the hotplug instance?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260608-counter_delegation-v6-0-285b72ed65a9@meta.com?part=14
next prev parent reply other threads:[~2026-06-09 6:33 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-09 6:01 [PATCH v6 00/21] Add Counter delegation ISA extension support Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:01 ` [PATCH v6 01/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:01 ` [PATCH v6 02/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:01 ` [PATCH v6 03/21] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:09 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 04/21] RISC-V: Define indirect CSR access helpers Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:15 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 05/21] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:01 ` [PATCH v6 06/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:09 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 07/21] RISC-V: Add Sscfg extension CSR definition Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:01 ` [PATCH v6 08/21] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:14 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 09/21] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:12 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 10/21] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:18 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 11/21] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:17 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 12/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:16 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 13/21] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:23 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 14/21] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:33 ` sashiko-bot [this message]
2026-06-09 6:01 ` [PATCH v6 15/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:23 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 16/21] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:21 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 17/21] RISC-V: perf: Add Qemu virt machine events Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:22 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 18/21] tools/perf: Support event code for arch standard events Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:18 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 19/21] tools/perf: Add RISC-V CounterIDMask event field Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:01 ` [PATCH v6 20/21] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:17 ` sashiko-bot
2026-06-09 6:01 ` [PATCH v6 21/21] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path Atish Patra
2026-06-09 6:01 ` Atish Patra
2026-06-09 6:20 ` sashiko-bot
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