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From: sashiko-bot@kernel.org
To: "Varadarajan Narayanan" <varadarajan.narayanan@oss.qualcomm.com>
Cc: vkoul@kernel.org, devicetree@vger.kernel.org,
	conor+dt@kernel.org, neil.armstrong@linaro.org,
	linux-phy@lists.infradead.org, olteanv@gmail.com,
	robh@kernel.org
Subject: Re: [PATCH v2 2/2] phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys
Date: Tue, 09 Jun 2026 09:34:25 +0000	[thread overview]
Message-ID: <20260609093426.CB1631F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260609-pcie-phy-v2-2-83bc80e79fa6@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The newly defined PHY initialization tables `ipq5210_gen3x1_pcie_ep_tx_tbl` and `ipq5210_gen3x1_pcie_ep_pcs_tbl` are never used, as the endpoint configuration mistakenly references tables from the ipq6018 SoC.
--

commit bf5e268631f81219e100892c439cbf010f5cd5f1
Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>

phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys

This patch adds support for a PCIe phys found on the Qualcomm ipq5210
platform.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
[ ... ]
> @@ -3613,6 +3712,49 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
[ ... ]
> +static const struct qmp_phy_cfg ipq5210_gen3x1_pciephy_cfg = {
[ ... ]
> +	.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
> +		.serdes		= ipq5210_gen3x1_pcie_ep_serdes_tbl,
> +		.serdes_num	= ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_serdes_tbl),
> +		.tx		= ipq6018_pcie_tx_tbl,
> +		.tx_num		= ARRAY_SIZE(ipq6018_pcie_tx_tbl),
> +		.rx		= ipq5210_gen3x1_pcie_ep_rx_tbl,
> +		.rx_num		= ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_rx_tbl),
> +		.pcs		= ipq6018_pcie_pcs_tbl,
> +		.pcs_num	= ARRAY_SIZE(ipq6018_pcie_pcs_tbl),

[Severity: High]
Are the newly added ipq5210_gen3x1_pcie_ep_tx_tbl and 
ipq5210_gen3x1_pcie_ep_pcs_tbl arrays intended to be used here?

This configuration assigns the tx and pcs fields to the ipq6018 arrays, which
appears to leave the new ipq5210 tx and pcs tables entirely unused. Could this
result in incorrect PHY hardware programming for the endpoint?

> +		.pcs_misc	= ipq5210_gen3x1_pcie_ep_pcs_misc_tbl,
> +		.pcs_misc_num	= ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_pcs_misc_tbl),
> +	},
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260609-pcie-phy-v2-0-83bc80e79fa6@oss.qualcomm.com?part=2

WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Varadarajan Narayanan" <varadarajan.narayanan@oss.qualcomm.com>
Cc: vkoul@kernel.org, devicetree@vger.kernel.org,
	conor+dt@kernel.org, neil.armstrong@linaro.org,
	linux-phy@lists.infradead.org, olteanv@gmail.com,
	robh@kernel.org
Subject: Re: [PATCH v2 2/2] phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys
Date: Tue, 09 Jun 2026 09:34:25 +0000	[thread overview]
Message-ID: <20260609093426.CB1631F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260609-pcie-phy-v2-2-83bc80e79fa6@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The newly defined PHY initialization tables `ipq5210_gen3x1_pcie_ep_tx_tbl` and `ipq5210_gen3x1_pcie_ep_pcs_tbl` are never used, as the endpoint configuration mistakenly references tables from the ipq6018 SoC.
--

commit bf5e268631f81219e100892c439cbf010f5cd5f1
Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>

phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys

This patch adds support for a PCIe phys found on the Qualcomm ipq5210
platform.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
[ ... ]
> @@ -3613,6 +3712,49 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
[ ... ]
> +static const struct qmp_phy_cfg ipq5210_gen3x1_pciephy_cfg = {
[ ... ]
> +	.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
> +		.serdes		= ipq5210_gen3x1_pcie_ep_serdes_tbl,
> +		.serdes_num	= ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_serdes_tbl),
> +		.tx		= ipq6018_pcie_tx_tbl,
> +		.tx_num		= ARRAY_SIZE(ipq6018_pcie_tx_tbl),
> +		.rx		= ipq5210_gen3x1_pcie_ep_rx_tbl,
> +		.rx_num		= ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_rx_tbl),
> +		.pcs		= ipq6018_pcie_pcs_tbl,
> +		.pcs_num	= ARRAY_SIZE(ipq6018_pcie_pcs_tbl),

[Severity: High]
Are the newly added ipq5210_gen3x1_pcie_ep_tx_tbl and 
ipq5210_gen3x1_pcie_ep_pcs_tbl arrays intended to be used here?

This configuration assigns the tx and pcs fields to the ipq6018 arrays, which
appears to leave the new ipq5210 tx and pcs tables entirely unused. Could this
result in incorrect PHY hardware programming for the endpoint?

> +		.pcs_misc	= ipq5210_gen3x1_pcie_ep_pcs_misc_tbl,
> +		.pcs_misc_num	= ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_pcs_misc_tbl),
> +	},
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260609-pcie-phy-v2-0-83bc80e79fa6@oss.qualcomm.com?part=2

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  reply	other threads:[~2026-06-09  9:34 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-09  9:22 [PATCH v2 0/2] Enable the QMP PCIe PHY present in Qualcomm ipq5210 SoC Varadarajan Narayanan
2026-06-09  9:22 ` Varadarajan Narayanan
2026-06-09  9:22 ` [PATCH v2 1/2] dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the ipq5210 QMP PCIe PHY Varadarajan Narayanan
2026-06-09  9:22   ` Varadarajan Narayanan
2026-06-09  9:22 ` [PATCH v2 2/2] phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys Varadarajan Narayanan
2026-06-09  9:22   ` Varadarajan Narayanan
2026-06-09  9:34   ` sashiko-bot [this message]
2026-06-09  9:34     ` sashiko-bot

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