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Tsirkin" , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Eric Blake , Markus Armbruster , Marcel Apfelbaum , Dmitry Fleytman , qemu-devel@nongnu.org Subject: Re: [PATCH v4 1/8] hw/acpi: Support extended GPE handling for additional ACPI devices Message-ID: <20260609145259.680fae5a@imammedo> In-Reply-To: <20260526042928.9203-2-lb.workbox@gmail.com> References: <20260526042928.9203-1-lb.workbox@gmail.com> <20260526042928.9203-2-lb.workbox@gmail.com> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, 26 May 2026 07:29:20 +0300 Leonid Bloch wrote: > This patch extends the GPE (General Purpose Event) handling to support > the maximum number of interrupts available based on the machine's GPE > register length, rather than being limited to the first 8 bits. > > This change is needed to support additional ACPI devices that will be > introduced in subsequent patches (Battery, AC adapter, and button devices). > These new devices require GPE event bits beyond the first 8, which were > previously not being properly handled by the event sending and SCI > (System Control Interrupt) update mechanisms. > > The actual number of available GPE interrupts varies by machine type: > - PIIX4: GPE_LEN = 4 (32 bits total across status and enable registers) > - ICH9: ICH9_PMIO_GPE0_LEN = 16 (128 bits total) > > The patch modifies: > - acpi_send_gpe_event(): Now properly propagates status bits across all > available GPE registers based on the machine's gpe.len value > - acpi_update_sci(): Checks all GPE registers for pending interrupts, > not just the first byte > > Note: A future enhancement could refactor the GPE handling to use the > bitmap API from bitops.h instead of the current manual bit manipulation, > which would provide a cleaner interface for these operations. > > Signed-off-by: Leonid Bloch > --- > hw/acpi/core.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/hw/acpi/core.c b/hw/acpi/core.c > index a6a62a742d..ad7abe568d 100644 > --- a/hw/acpi/core.c > +++ b/hw/acpi/core.c > @@ -733,19 +733,32 @@ uint32_t acpi_gpe_ioport_readb(ACPIREGS *ar, uint32_t addr) > void acpi_send_gpe_event(ACPIREGS *ar, qemu_irq irq, > AcpiEventStatusBits status) > { > - ar->gpe.sts[0] |= status; > + int i; > + AcpiEventStatusBits st = status; > + > + for (i = 0; i < ar->gpe.len / 2; i++) { > + ar->gpe.sts[i] |= st; > + st >>= TYPE_WIDTH(ar->gpe.sts[0]); > + } Function is ever called with only one bit set at a time. I'd suggest to add assert to guard for multiple bits and use existing bitops instead of open-codding the loop. > acpi_update_sci(ar, irq); > } > > void acpi_update_sci(ACPIREGS *regs, qemu_irq irq) > { > int sci_level, pm1a_sts; > + bool gpe_sci = false; > + int i; > > pm1a_sts = acpi_pm1_evt_get_sts(regs); > > + for (i = 0; i < regs->gpe.len / 2; i++) { > + gpe_sci = gpe_sci || !!(regs->gpe.sts[i] & regs->gpe.en[i]); > + } > + > sci_level = ((pm1a_sts & > regs->pm1.evt.en & ACPI_BITMASK_PM1_COMMON_ENABLED) != 0) || > - ((regs->gpe.sts[0] & regs->gpe.en[0]) != 0); > + gpe_sci; > > qemu_set_irq(irq, sci_level); >