Re: [PATCH 3/3] arm64: dts: cortina-access: Add DTS for CA8289 SoC and Venus board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Use of discouraged `clock-frequency` property in the ARMv8 timer node.
- [Low] Missing root `#address-cells` and `#size-cells` in SoC DTSI.
--

commit bb6d4b41e4c489bdce2ba3142178fa3654514276
Author: Jason Li <jason.lee651024@gmail.com>

arm64: dts: cortina-access: Add DTS for CA8289 SoC and Venus board

Add SoC DTSI for the Cortina-Access CA8289 (Venus) and a board DTS for
the Venus engineering board. The description covers the minimum set of
hardware nodes needed to boot a kernel with an INITRD rootfs.

> diff --git a/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi b/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
> new file mode 100644
> index 0000000000000..8e7ffcf4ccab4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for Cortina Access CA8289 SoC
> + *
> + * Copyright (C) 2026, Cortina Access Inc.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {

[Severity: Low]
Should the root node of this DTSI include its own #address-cells and
#size-cells declarations?

While the top-level ca8289-engboard.dts provides these, defining several
top-level nodes (like gic, uart0, uart1) that use 64-bit addresses relies
on the board file to satisfy the DTSI's cell size requirements. Could
these be added to the DTSI root node so it remains self-contained?

> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;

[ ... ]

> +	/* See Documentation/devicetree/bindings/timer/arm,arch_timer.yaml */
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +		clock-frequency = <25000000>;

[Severity: Medium]
Is this clock-frequency property strictly necessary for this new SoC?

For ARMv8 architectures, the system timer frequency should typically be
programmed into the CNTFRQ_EL0 register by the boot firmware (e.g., TF-A)
on all CPUs.

The devicetree clock-frequency property is generally treated as a workaround
for legacy firmware that cannot be modified. For new SoC ports, can the boot
firmware be updated to properly initialize CNTFRQ_EL0 instead?

> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260610112821.3030099-1-jason.li@cortina-access.com?part=3