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[80.230.85.71]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606c0fc493sm1745039f8f.25.2026.06.11.13.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 13:52:23 -0700 (PDT) Date: Thu, 11 Jun 2026 16:52:20 -0400 From: "Michael S. Tsirkin" To: Peter Xu Cc: Peter Maydell , Gavin Shan , Pavel Hrdina , Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, jugraham@redhat.com, shan.gavin@gmail.com, Alex Williamson , David Hildenbrand Subject: Re: [PATCH RFCv1] virtio: Inherit max bounce buffer size from bus parent if possible Message-ID: <20260611164624-mutt-send-email-mst@kernel.org> References: <20260611093049-mutt-send-email-mst@kernel.org> <20260611110156-mutt-send-email-mst@kernel.org> <20260611114811-mutt-send-email-mst@kernel.org> <20260611123952-mutt-send-email-mst@kernel.org> <20260611130037-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jun 11, 2026 at 02:20:54PM -0400, Peter Xu wrote: > On Thu, Jun 11, 2026 at 01:02:34PM -0400, Michael S. Tsirkin wrote: > > On Thu, Jun 11, 2026 at 05:53:54PM +0100, Peter Maydell wrote: > > > On Thu, 11 Jun 2026 at 17:42, Michael S. Tsirkin wrote: > > > > > > > > On Thu, Jun 11, 2026 at 05:16:09PM +0100, Peter Maydell wrote: > > > > > On Thu, 11 Jun 2026 at 16:57, Michael S. Tsirkin wrote: > > > > > > Then I'd like to see an example where we have an actual good reason > > > > > > to do execute arbitrary width accesses on device RAM when the > > > > > > driver does not execute them, please. > > > > > > > > > > That's the case we started with, with this GPU where the > > > > > virtio data structures are in this PCI BAR. We want the > > > > > virtio backend to have the freedom to say "I'm just going > > > > > to assume the ring buffer etc is in RAM, and I don't need to > > > > > care about carefully ensuring that I only do word accesses". > > > > > > > > virtio backend does not need to assume anything. any spec > > > > compliant guest guarantees it. any address given to > > > > a virtio device is ram. > > > > > > OK, but how do we tell if the mmap() PCI BAR we have is RAM > > > or not ? Some of them are, some of them aren't... > > > > > > -- PMM > > > > We don't care? If guest asked a virtio device to access > > memory then that memory better support accesses guest > > requested, and on virtio that means any width. > > Yes that's also my understanding that QEMU shouldn't care, if on bare metal > if it is a grey area with undefined behavior, then QEMU should also be fine > to make it undefined. > > Only one (IMHO, very slight..) concern is, if such "undefined behavior" > operation may crash QEMU rather than causing a sigbus like what normally > would happen on a bare metal. bus errors are uncommon on bare metal. they aren't usually handled all that well. > I'll put that discussion at last since I > don't know if it's that important. > > So taking that e1000 bug into account, Won't the patch I sent resolve e1000 too? > looks like we have more of such user > that wants explicit control over the memory operations, likely with > attibutes: > > - Aligned only > > - No vectored inst > > - No possible duplication (perhaps it means, only use atomic access??? per > PeterM's explanation in another email) > > I wonder if we should do this by default to all IOs, I think it might have > an unwanted impact on general perf. One idea is we can introduce a new bit > in MemTxAttrs: say, mmio_strict, which will follow above stricter rule of > doing IO. > > Then for ram_device, when doing memory access we should also use the same > set, hence something like: > > if (memory_access_is_direct(mr, ...)) { > if (MemTxAttrs.mmio_strict || memory_region_is_ram_device(mr)) { > memmove_strict_mmio(); // or memmove_no_vector(), or ... > } > } > > I also want to bring us to the same page on differenciating two things: > > - about direct access definition: so far, I want to define this almost as > "it is directly accessible from host virtual address space". It means > ram_device definitely falls into this category, so it's a sub-category > only but enforces strict mmio as above > > - bounce buffer: I want to make sure we're on the same page this is > something totally solving different problem of what we're looking at for > ram_device. Essentially this is only needed if mem is not "direct > access". Otherwise we shouldn't need it (including ram_device). I think ram_device_direct_access is a hack that should go away. It's a work around for a memory core bug that we should just fix. > I'm not sure if above sounds reasonable. The hope is with that we should > fix both this GPU and e1000 issues (e1000, and maybe other places, needs to > start passing MemTxAttrs.mmio_strict, though, if we want to keep the > default to be still fast-path to use memcpy()/memmove()?). > > Thanks, > > ========================= > > Two cases here on the concern: > > (1) if fully emulated device, non-issue afaiu because whatever DMA does > (with vectored ops) will only apply to QEMU process (like a bounce > buffer..) so it won't crash, > > (2) if it's a VFIO device (not the GPU case, but when like realtek and some > guest driver registers it as a DMA target), logically the guest should > receive a bus error, but for QEMU's case it may crash QEMU with SIGBUS: what and why would crash qemu? > sigbus_handler() doesn't process anything except memory failures so far, it > seems. The right thing might be that we forward this sigbus to guest, but > I didn't check further. > > But I don't know if it would really happen, better verify it, and even if > it will happen I still think it's a very niche security use case to cover > so far. Doesn't seem to be a blocker to fix a real perf problem first with > RAM-like GPU devices. > > -- > Peter Xu