From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DDDBCD98CE for ; Fri, 12 Jun 2026 15:52:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wY49s-00017V-Mq; Fri, 12 Jun 2026 11:51:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wY49o-00017H-Af for qemu-devel@nongnu.org; Fri, 12 Jun 2026 11:50:56 -0400 Received: from sea.source.kernel.org ([172.234.252.31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wY49m-0008Ck-Ec for qemu-devel@nongnu.org; Fri, 12 Jun 2026 11:50:56 -0400 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 90DDF44328; Fri, 12 Jun 2026 15:50:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0D191F000E9; Fri, 12 Jun 2026 15:50:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781279453; bh=ka4VbvNFDIvk3wX9UUytgcfG8jW4A6Dg6ZEgYbgSxww=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=VPLnw73iJaxTG1csdQVcEzPl7Wlz2vraQxd/Lu1TZLLxrc7qHqx3S9KmdDehGPVg5 bxz4gfwcuq+c3Xkab914LRJfQZcBfSv5x3O8O126rvJcNCcS9C2X35Eew0DTtMtcze hSk/o5Rwu35zoBUOfB2d0fU6XuYw9kOoan9Uto5dn12KIQrnLk1DP+i1eQcg3GQnUp JBOWrsOQUOPSVsXQzofmIaR71OhFQFy6cIpl3laIN64fAvPMrSugL0+ZK+lXOGFpm/ k/wqP4l5BcXHKWK5Qic1EjCPuJOsirz/ASLIbccQcYaEX/FB7H/1nDCYOnr8gGlH2j YnKLtWCiByTeg== From: Helge Deller To: Stefan Hajnoczi , qemu-devel@nongnu.org Cc: Helge Deller , Pierrick Bouvier , Laurent Vivier , Max Filippov , Matt Turner , Richard Henderson Subject: [PULL 3/4] target/xtensa: add cpu_set_fcr/fsr helpers to sync fp_status Date: Fri, 12 Jun 2026 17:50:42 +0200 Message-ID: <20260612155043.3552-4-deller@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260612155043.3552-1-deller@kernel.org> References: <20260612155043.3552-1-deller@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=172.234.252.31; envelope-from=deller@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Matt Turner Factor FCR→fp_status and FSR→fp_status synchronisation out of the wur_fpu{2k,}_fcr/wur_fpu_fsr helpers into cpu_set_fcr(), cpu_set_fsr(), and cpu_get_fsr(). Signal delivery code needs to restore the FP rounding mode and exception flags without duplicating the flag-mapping tables. cpu_set_fcr() applies the union mask 0xfffff07f (superset of the wur_fpu_fcr mask 0x0000007f and the wur_fpu2k_fcr mask 0xfffff07f) so that FCR bits valid only on fpu2k configs are preserved while MBZ bits 7-11 are always cleared. Signed-off-by: Matt Turner Reviewed-by: Richard Henderson Signed-off-by: Helge Deller --- target/xtensa/cpu.h | 4 +++ target/xtensa/fpu_helper.c | 71 +++++++++++++++++++++----------------- 2 files changed, 44 insertions(+), 31 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 75cfeee6e3..442e98bd1b 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -642,6 +642,10 @@ static inline void xtensa_select_static_vectors(CPUXtensaState *env, } void xtensa_runstall(CPUXtensaState *env, bool runstall); +uint32_t cpu_get_fsr(CPUXtensaState *env); +void cpu_set_fcr(CPUXtensaState *env, uint32_t v); +void cpu_set_fsr(CPUXtensaState *env, uint32_t v); + #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) #define XTENSA_OPTION_ALL (~(uint64_t)0) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 5358060c50..2e51cabe3f 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -64,46 +64,39 @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) &env->fp_status); } -void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) +uint32_t cpu_get_fsr(CPUXtensaState *env) { - static const int rounding_mode[] = { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down, - }; + uint32_t flags = 0; + int fef = get_float_exception_flags(&env->fp_status); + unsigned i; - env->uregs[FCR] = v & 0xfffff07f; - set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); + for (i = 0; i < ARRAY_SIZE(xtensa_fp_flag_map); ++i) { + if (fef & xtensa_fp_flag_map[i].softfloat_fp_flag) { + flags |= xtensa_fp_flag_map[i].xtensa_fp_flag; + } + } + return flags << XTENSA_FSR_FLAGS_SHIFT; } -void HELPER(wur_fpu_fcr)(CPUXtensaState *env, uint32_t v) +void cpu_set_fcr(CPUXtensaState *env, uint32_t v) { - static const int rounding_mode[] = { + static const FloatRoundMode rounding_mode[] = { float_round_nearest_even, float_round_to_zero, float_round_up, float_round_down, }; - if (v & 0xfffff000) { - qemu_log_mask(LOG_GUEST_ERROR, - "MBZ field of FCR is written non-zero: %08x\n", v); - } - env->uregs[FCR] = v & 0x0000007f; + env->uregs[FCR] = v & 0xfffff07f; set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); } -void HELPER(wur_fpu_fsr)(CPUXtensaState *env, uint32_t v) +void cpu_set_fsr(CPUXtensaState *env, uint32_t v) { uint32_t flags = v >> XTENSA_FSR_FLAGS_SHIFT; int fef = 0; unsigned i; - if (v & 0xfffff000) { - qemu_log_mask(LOG_GUEST_ERROR, - "MBZ field of FSR is written non-zero: %08x\n", v); - } env->uregs[FSR] = v & 0x00000f80; for (i = 0; i < ARRAY_SIZE(xtensa_fp_flag_map); ++i) { if (flags & xtensa_fp_flag_map[i].xtensa_fp_flag) { @@ -113,19 +106,35 @@ void HELPER(wur_fpu_fsr)(CPUXtensaState *env, uint32_t v) set_float_exception_flags(fef, &env->fp_status); } -uint32_t HELPER(rur_fpu_fsr)(CPUXtensaState *env) +void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) { - uint32_t flags = 0; - int fef = get_float_exception_flags(&env->fp_status); - unsigned i; + cpu_set_fcr(env, v); +} - for (i = 0; i < ARRAY_SIZE(xtensa_fp_flag_map); ++i) { - if (fef & xtensa_fp_flag_map[i].softfloat_fp_flag) { - flags |= xtensa_fp_flag_map[i].xtensa_fp_flag; - } +void HELPER(wur_fpu_fcr)(CPUXtensaState *env, uint32_t v) +{ + if (v & 0xfffff000) { + qemu_log_mask(LOG_GUEST_ERROR, + "MBZ field of FCR is written non-zero: %08x\n", v); } - env->uregs[FSR] = flags << XTENSA_FSR_FLAGS_SHIFT; - return flags << XTENSA_FSR_FLAGS_SHIFT; + cpu_set_fcr(env, v & 0x0000007f); +} + +void HELPER(wur_fpu_fsr)(CPUXtensaState *env, uint32_t v) +{ + if (v & 0xfffff000) { + qemu_log_mask(LOG_GUEST_ERROR, + "MBZ field of FSR is written non-zero: %08x\n", v); + } + cpu_set_fsr(env, v); +} + +uint32_t HELPER(rur_fpu_fsr)(CPUXtensaState *env) +{ + uint32_t fsr = cpu_get_fsr(env); + + env->uregs[FSR] = fsr; + return fsr; } float64 HELPER(abs_d)(float64 v) -- 2.54.0