From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E83BDCD98CF for ; Fri, 12 Jun 2026 22:48:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=sZ8zv1h9vTqxIWN/kyWnqAytOew5Axzx7GoxuJXRb+s=; b=zmmlrNKaaTW4T+TWDlTkZXAz4J 7orMvN9qtu2aP1ONygczplzzAeKQM6iQ0hDMf12QfjnVuFELGVMRgC4+4o++TtXzmG+8r9XFDEcmm BN+1rBYqkobh0c2FJWj3PUDvyAV/ALTdbJNOo42WQXy2uttYNRkrta4nJY++LyhHLw5nCOQFlUKLR tppTf8TpfPByjSHYvfSA75bURfTLIATeDPNY12RvVwF/noCGCKDawJN5UwlL7TiotVMQy5lJmwsLi GxolTKATFelPnSCQM38bpqJNdaApb/z32dWeQnP0uI+0QZHCwm0dfylAIM8Vj8JbzpTGDIUHLU4sm aPQvlUhA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wYAfv-0000000BisB-0xav; Fri, 12 Jun 2026 22:48:31 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wYAft-0000000Birw-0tpA for linux-arm-kernel@lists.infradead.org; Fri, 12 Jun 2026 22:48:29 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 4F58C60008; Fri, 12 Jun 2026 22:48:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 07BC41F000E9; Fri, 12 Jun 2026 22:48:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781304508; bh=sZ8zv1h9vTqxIWN/kyWnqAytOew5Axzx7GoxuJXRb+s=; h=From:To:Cc:Subject:Date; b=Wzq/qGDwR/S27eZeXfUkKaYYM9YhvcxpaWjonZHZ1+5OQDSWgs1xXto6u+vMvAxf7 pFVrfjMLlN3l2nxNXrqL1opIh+HgqkzrSCyKW7s3sdxE3iS4nP/b0442fwkgNG2EiC zqKug41i1HlGtnEaLk7HKqz0VdOHVEudtly81GfgCCADTgldRbf8xtmvbk2LUAv+ku 2AxUgW7gRvfSW4qSHiQJfv0FKDHSXpklXbWnvNnJfYKRfwjS3F0gxULF6mlpAoYsLQ A7RavZtrbSNO85p7krTiyvFD1rMSkBiQpz807Of22d0npfxyNKZdF3qz0xn05JA62z LqM44TQ1p9/Zw== From: Bjorn Andersson To: Stephen Boyd , linux-clk@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Vivek Aknurwar , Luca Weiss , Jagadeesh Kona , Krzysztof Kozlowski , Luo Jie , Bartosz Golaszewski , Kathiravan Thirumoorthy , Alexander Koskovich , Biswapriyo Nath , Konrad Dybcio , Phillip Varney Subject: [GIT PULL] Qualcomm clock updates for v7.2 Date: Fri, 12 Jun 2026 17:48:25 -0500 Message-ID: <20260612224825.852551-1-andersson@kernel.org> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The following changes since commit 254f49634ee16a731174d2ae34bc50bd5f45e731: Linux 7.1-rc1 (2026-04-26 14:19:00 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-clk-for-7.2 for you to fetch changes up to e108373c54fbc844b7f541c6fd7ecb31772afd3c: clk: qcom: regmap-phy-mux: Rework the implementation (2026-06-08 09:17:24 -0500) ---------------------------------------------------------------- Qualcomm clock updates for v7.2 Introduce global, TCSR, and RPMh clock controllers for the Hawi mobile SoC. Introduce GX clock for Milos, and ensure that camera clock controller votes for interconnect bandwidth in order to ensure the TOP_GDSC can be turned on. Introduce camera and video clock controllers for Hamoa and Purwa. Reduce the max_register of the display clock controller to avoid regmap attemting to dump protected registers. Introduce global clock controller for the IPQ9650 SoC and add IPQ5332 support to the cmnpll driver. Add missing USB2 PHY reset to the Nord NegCC. Rework the PHY mux clock implementation as necessary for upcoming USB4 support. ---------------------------------------------------------------- Alexander Koskovich (1): clk: qcom: clk-rpmh: Make all VRMs optional Bartosz Golaszewski (2): dt-bindings: clock: qcom: add the definition for the USB2 PHY reset clk: qcom: nord: negcc: add support for the USB2 PHY reset Biswapriyo Nath (1): dt-bindings: clock: qcom,sm6125-dispcc: reference qcom,gcc.yaml Bjorn Andersson (2): Merge branch '20260507-ipq9650_boot_to_shell-v3-1-62742b49c991@oss.qualcomm.com' into clk-for-7.2 Merge branch '20260106-qcom_ipq5332_cmnpll-v2-2-f9f7e4efbd79@oss.qualcomm.com' into clk-for-7.2 Jagadeesh Kona (5): dt-bindings: clock: qcom: Add X1P42100 video clock controller dt-bindings: clock: qcom: Add X1P42100 camera clock controller clk: qcom: videocc-x1p42100: Add support for video clock controller clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks clk: qcom: camcc-x1p42100: Add support for camera clock controller Kathiravan Thirumoorthy (2): dt-bindings: clock: add Qualcomm IPQ9650 GCC clk: qcom: add Global Clock controller (GCC) driver for IPQ9650 SoC Konrad Dybcio (1): clk: qcom: regmap-phy-mux: Rework the implementation Krzysztof Kozlowski (3): clk: qcom: dispcc-x1e80100: Fix (possibly) dumping regmap clk: qcom: Constify qcom_cc_driver_data and list of critical CBCR registers dt-bindings: clock: qcom,kaanapali-gxclkctl: Correctly use additionalProperties Luca Weiss (6): dt-bindings: clock: qcom: document the Milos GX clock controller clk: qcom: Add support for GXCLK for Milos interconnect: Add devm_of_icc_get_by_index() as exported API for users dt-bindings: clock: qcom,milos-camcc: Document interconnect path clk: qcom: gdsc: Support enabling interconnect path for power domain clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC Luo Jie (3): dt-bindings: clock: qcom: Add CMN PLL support for IPQ5332 SoC clk: qcom: cmnpll: Account for reference clock divider clk: qcom: cmnpll: Add IPQ5332 SoC support Phillip Varney (1): clk: qcom: a53: Corrected frequency multiplier for 1152MHz Vivek Aknurwar (7): dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for Hawi dt-bindings: clock: qcom: Add Hawi TCSR clock controller dt-bindings: clock: qcom: Add Hawi global clock controller clk: qcom: rpmh: Add support for Hawi RPMH clocks clk: qcom: Add Hawi TCSR clock controller driver clk: qcom: clk-alpha-pll: Add support for Taycan EHA_T PLL clk: qcom: Add support for global clock controller on Hawi .../bindings/clock/qcom,dispcc-sm6125.yaml | 17 +- .../devicetree/bindings/clock/qcom,hawi-gcc.yaml | 63 + .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + .../bindings/clock/qcom,ipq9650-gcc.yaml | 68 + .../bindings/clock/qcom,kaanapali-gxclkctl.yaml | 2 +- .../bindings/clock/qcom,milos-camcc.yaml | 8 + .../bindings/clock/qcom,milos-gxclkctl.yaml | 61 + .../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + .../bindings/clock/qcom,sm8450-videocc.yaml | 3 + .../bindings/clock/qcom,sm8550-tcsr.yaml | 2 + .../bindings/clock/qcom,x1e80100-camcc.yaml | 1 + drivers/clk/qcom/Kconfig | 48 + drivers/clk/qcom/Makefile | 7 +- drivers/clk/qcom/a53-pll.c | 2 +- drivers/clk/qcom/camcc-milos.c | 7 + drivers/clk/qcom/camcc-x1e80100.c | 64 + drivers/clk/qcom/camcc-x1p42100.c | 2223 ++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 6 + drivers/clk/qcom/clk-regmap-phy-mux.c | 52 +- drivers/clk/qcom/clk-rpmh.c | 41 +- drivers/clk/qcom/dispcc-x1e80100.c | 2 +- drivers/clk/qcom/gcc-hawi.c | 3657 ++++++++++++++++++++ drivers/clk/qcom/gcc-ipq9650.c | 3445 ++++++++++++++++++ drivers/clk/qcom/gcc-nord.c | 2 +- drivers/clk/qcom/gdsc.c | 33 + drivers/clk/qcom/gdsc.h | 5 + drivers/clk/qcom/gpucc-sm8750.c | 4 +- drivers/clk/qcom/gxclkctl-kaanapali.c | 1 + drivers/clk/qcom/ipq-cmn-pll.c | 30 +- drivers/clk/qcom/negcc-nord.c | 3 +- drivers/clk/qcom/nwgcc-nord.c | 4 +- drivers/clk/qcom/segcc-nord.c | 2 +- drivers/clk/qcom/tcsrcc-hawi.c | 158 + drivers/clk/qcom/videocc-x1p42100.c | 585 ++++ drivers/interconnect/core.c | 20 + include/dt-bindings/clock/qcom,hawi-gcc.h | 253 ++ include/dt-bindings/clock/qcom,hawi-tcsrcc.h | 16 + include/dt-bindings/clock/qcom,ipq5332-cmn-pll.h | 19 + include/dt-bindings/clock/qcom,ipq9650-gcc.h | 172 + include/dt-bindings/clock/qcom,nord-negcc.h | 1 + include/dt-bindings/clock/qcom,rpmh.h | 2 + include/dt-bindings/clock/qcom,x1e80100-camcc.h | 3 + include/dt-bindings/clock/qcom,x1p42100-videocc.h | 48 + include/dt-bindings/reset/qcom,ipq9650-gcc.h | 215 ++ include/linux/interconnect.h | 6 + 45 files changed, 11313 insertions(+), 50 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml create mode 100644 Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml create mode 100644 drivers/clk/qcom/camcc-x1p42100.c create mode 100644 drivers/clk/qcom/gcc-hawi.c create mode 100644 drivers/clk/qcom/gcc-ipq9650.c create mode 100644 drivers/clk/qcom/tcsrcc-hawi.c create mode 100644 drivers/clk/qcom/videocc-x1p42100.c create mode 100644 include/dt-bindings/clock/qcom,hawi-gcc.h create mode 100644 include/dt-bindings/clock/qcom,hawi-tcsrcc.h create mode 100644 include/dt-bindings/clock/qcom,ipq5332-cmn-pll.h create mode 100644 include/dt-bindings/clock/qcom,ipq9650-gcc.h create mode 100644 include/dt-bindings/clock/qcom,x1p42100-videocc.h create mode 100644 include/dt-bindings/reset/qcom,ipq9650-gcc.h