From: sashiko-bot@kernel.org
To: "Paul Kocialkowski" <paulk@sys-base.io>
Cc: robh@kernel.org, linux-sunxi@lists.linux.dev,
conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v10 5/6] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
Date: Sat, 13 Jun 2026 15:41:31 +0000 [thread overview]
Message-ID: <20260613154131.A62201F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260613152655.212490-6-paulk@sys-base.io>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `csi0` node introduces the `interconnects` and `interconnect-names` properties, but these are not defined in the corresponding dt-binding schema `allwinner,sun6i-a31-csi.yaml`.
--
commit 6348731e0b0149fecdb9ccb7d05f8577710a1724
Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
This commit adds MIPI CSI-2 support for the V3s SoC by introducing nodes
for CSI0, the MIPI CSI-2 bridge, and the D-PHY. The CSI0 node includes
interconnect properties to inherit the proper DMA offsets.
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> index 02d6c62b3874e..03a1739683b16 100644
> --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
[ ... ]
> @@ -671,6 +671,79 @@ gic: interrupt-controller@1c81000 {
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> + csi0: camera@1cb0000 {
> + compatible = "allwinner,sun8i-v3s-csi";
> + reg = <0x01cb0000 0x1000>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI_SCLK>,
> + <&ccu CLK_DRAM_CSI>;
> + clock-names = "bus", "mod", "ram";
> + resets = <&ccu RST_BUS_CSI>;
> + interconnects = <&mbus 5>;
> + interconnect-names = "dma-mem";
[Severity: Low]
Will adding these properties cause a dtbs_check validation warning?
The interconnects and interconnect-names properties do not appear to be
defined in the corresponding dt-binding schema at
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml.
Because that schema enforces additionalProperties: false, introducing
undocumented properties here might result in a validation failure. Should
the schema be updated alongside this patch to allow these interconnect
properties?
> + status = "disabled";
> +
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260613152655.212490-1-paulk@sys-base.io?part=5
next prev parent reply other threads:[~2026-06-13 15:41 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-13 15:26 [PATCH v10 0/6] Allwinner A31/A83T MIPI CSI-2 and A31 ISP / Platform Support Paul Kocialkowski
2026-06-13 15:26 ` [PATCH v10 1/6] dt-bindings: sun8i-v3s-ccu: Export MBUS and DRAM clocks to the public header Paul Kocialkowski
2026-06-13 18:20 ` Krzysztof Kozlowski
2026-06-13 15:26 ` [PATCH v10 2/6] clk: sunxi-ng: v3s: Remove exported clock definitions Paul Kocialkowski
2026-06-13 15:26 ` [PATCH v10 3/6] ARM: dts: sun8i: v3s: Add mbus node to represent the interconnect Paul Kocialkowski
2026-06-13 15:26 ` [PATCH v10 4/6] dt-bindings: sun6i-a31-mipi-dphy: Add V3s SoC compatible entry Paul Kocialkowski
2026-06-13 15:35 ` sashiko-bot
2026-06-13 16:11 ` Paul Kocialkowski
2026-06-13 18:22 ` Krzysztof Kozlowski
2026-06-13 15:26 ` [PATCH v10 5/6] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support Paul Kocialkowski
2026-06-13 15:41 ` sashiko-bot [this message]
2026-06-13 16:04 ` Paul Kocialkowski
2026-06-13 15:26 ` [PATCH v10 6/6] ARM: dts: sun8i: v3s: Add support for the ISP Paul Kocialkowski
2026-06-13 17:39 ` sashiko-bot
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