From: kernel test robot <lkp@intel.com>
To: Roman Li <Roman.Li@amd.com>
Cc: oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org,
Alex Deucher <alexander.deucher@amd.com>
Subject: drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c:1114 dcn42_clk_mgr_construct() warn: inconsistent indenting
Date: Sat, 13 Jun 2026 18:46:35 +0800 [thread overview]
Message-ID: <202606131804.W0GAT9Zv-lkp@intel.com> (raw)
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 062871f1371b2e02a272ff5279c6479aff0a37ef
commit: 6b2dd7d37badd8bf076875397f9f39b494258ca7 drm/amd/display: Enable dcn42 DC
date: 4 months ago
config: i386-randconfig-141-20260611 (https://download.01.org/0day-ci/archive/20260613/202606131804.W0GAT9Zv-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
smatch: v0.5.0-9185-gbcc58b9c
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Fixes: 6b2dd7d37bad ("drm/amd/display: Enable dcn42 DC")
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202606131804.W0GAT9Zv-lkp@intel.com/
New smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c:1114 dcn42_clk_mgr_construct() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn42/dcn42_hwseq.c:560 dcn42_program_rmcm_luts() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn42/dcn42_hwseq.c:1060 dcn42_optimize_bandwidth() warn: inconsistent indenting
Old smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn42/dcn42_hwseq.c:279 dcn42_init_hw() error: we previously assumed 'dc->res_pool->funcs->update_bw_bounding_box' could be null (see line 274)
vim +1114 drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
bd096a56da7cad Roman Li 2026-02-02 1077
bd096a56da7cad Roman Li 2026-02-02 1078 void dcn42_clk_mgr_construct(
bd096a56da7cad Roman Li 2026-02-02 1079 struct dc_context *ctx,
bd096a56da7cad Roman Li 2026-02-02 1080 struct clk_mgr_dcn42 *clk_mgr,
bd096a56da7cad Roman Li 2026-02-02 1081 struct pp_smu_funcs *pp_smu,
bd096a56da7cad Roman Li 2026-02-02 1082 struct dccg *dccg)
bd096a56da7cad Roman Li 2026-02-02 1083 {
bd096a56da7cad Roman Li 2026-02-02 1084 clk_mgr->base.base.ctx = ctx;
bd096a56da7cad Roman Li 2026-02-02 1085 clk_mgr->base.base.funcs = &dcn42_funcs;
bd096a56da7cad Roman Li 2026-02-02 1086 clk_mgr->base.regs = &clk_mgr_regs_dcn42;
bd096a56da7cad Roman Li 2026-02-02 1087 clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn42;
bd096a56da7cad Roman Li 2026-02-02 1088 clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn42;
bd096a56da7cad Roman Li 2026-02-02 1089
bd096a56da7cad Roman Li 2026-02-02 1090 clk_mgr->base.pp_smu = pp_smu;
bd096a56da7cad Roman Li 2026-02-02 1091
bd096a56da7cad Roman Li 2026-02-02 1092 clk_mgr->base.dccg = dccg;
bd096a56da7cad Roman Li 2026-02-02 1093 clk_mgr->base.dfs_bypass_disp_clk = 0;
bd096a56da7cad Roman Li 2026-02-02 1094
bd096a56da7cad Roman Li 2026-02-02 1095 clk_mgr->base.dprefclk_ss_percentage = 0;
bd096a56da7cad Roman Li 2026-02-02 1096 clk_mgr->base.dprefclk_ss_divider = 1000;
bd096a56da7cad Roman Li 2026-02-02 1097 clk_mgr->base.ss_on_dprefclk = false;
bd096a56da7cad Roman Li 2026-02-02 1098 clk_mgr->base.dfs_ref_freq_khz = 48000; /*sync with pmfw*/
bd096a56da7cad Roman Li 2026-02-02 1099
bd096a56da7cad Roman Li 2026-02-02 1100 clk_mgr->smu_wm_set.wm_set = (struct dcn42_watermarks *)dm_helpers_allocate_gpu_mem(
bd096a56da7cad Roman Li 2026-02-02 1101 clk_mgr->base.base.ctx,
bd096a56da7cad Roman Li 2026-02-02 1102 DC_MEM_ALLOC_TYPE_GART,
bd096a56da7cad Roman Li 2026-02-02 1103 sizeof(struct dcn42_watermarks),
bd096a56da7cad Roman Li 2026-02-02 1104 &clk_mgr->smu_wm_set.mc_address.quad_part);
bd096a56da7cad Roman Li 2026-02-02 1105
bd096a56da7cad Roman Li 2026-02-02 1106 ASSERT(clk_mgr->smu_wm_set.wm_set);
bd096a56da7cad Roman Li 2026-02-02 1107
bd096a56da7cad Roman Li 2026-02-02 1108 /* Changed from DCN3.2_clock_frequency doc to match
bd096a56da7cad Roman Li 2026-02-02 1109 * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
bd096a56da7cad Roman Li 2026-02-02 1110 * dprefclk DID divider
bd096a56da7cad Roman Li 2026-02-02 1111 */
bd096a56da7cad Roman Li 2026-02-02 1112 clk_mgr->base.base.dprefclk_khz = 600000;
bd096a56da7cad Roman Li 2026-02-02 1113
bd096a56da7cad Roman Li 2026-02-02 @1114 clk_mgr->base.smu_present = false;
bd096a56da7cad Roman Li 2026-02-02 1115
bd096a56da7cad Roman Li 2026-02-02 1116 if (ctx->dc_bios->integrated_info) {
bd096a56da7cad Roman Li 2026-02-02 1117 clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq;
bd096a56da7cad Roman Li 2026-02-02 1118
bd096a56da7cad Roman Li 2026-02-02 1119 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
bd096a56da7cad Roman Li 2026-02-02 1120 dcn42_bw_params.wm_table = lpddr5_wm_table;
bd096a56da7cad Roman Li 2026-02-02 1121 else
bd096a56da7cad Roman Li 2026-02-02 1122 dcn42_bw_params.wm_table = ddr5_wm_table;
bd096a56da7cad Roman Li 2026-02-02 1123 dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type;
bd096a56da7cad Roman Li 2026-02-02 1124 dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4;
bd096a56da7cad Roman Li 2026-02-02 1125 dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 4;
bd096a56da7cad Roman Li 2026-02-02 1126 }
bd096a56da7cad Roman Li 2026-02-02 1127 /* in case we don't get a value from the BIOS, use default */
bd096a56da7cad Roman Li 2026-02-02 1128 if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
bd096a56da7cad Roman Li 2026-02-02 1129 clk_mgr->base.base.dentist_vco_freq_khz = 3000000; /* 3000MHz */
bd096a56da7cad Roman Li 2026-02-02 1130
bd096a56da7cad Roman Li 2026-02-02 1131 /* Saved clocks configured at boot for debug purposes */
bd096a56da7cad Roman Li 2026-02-02 1132 dcn42_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
bd096a56da7cad Roman Li 2026-02-02 1133
bd096a56da7cad Roman Li 2026-02-02 1134 if (clk_mgr->base.smu_present)
bd096a56da7cad Roman Li 2026-02-02 1135 clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base);
bd096a56da7cad Roman Li 2026-02-02 1136 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
bd096a56da7cad Roman Li 2026-02-02 1137 dce_clock_read_ss_info(&clk_mgr->base);
bd096a56da7cad Roman Li 2026-02-02 1138 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
bd096a56da7cad Roman Li 2026-02-02 1139
bd096a56da7cad Roman Li 2026-02-02 1140 dcn42_read_ss_info_from_lut(&clk_mgr->base);
bd096a56da7cad Roman Li 2026-02-02 1141
bd096a56da7cad Roman Li 2026-02-02 1142 clk_mgr->base.base.bw_params = &dcn42_bw_params;
bd096a56da7cad Roman Li 2026-02-02 1143 }
bd096a56da7cad Roman Li 2026-02-02 1144
:::::: The code at line 1114 was first introduced by commit
:::::: bd096a56da7cad1c93c0138a64478b43f5a94736 drm/amd/display: Add dcn42 DC resources
:::::: TO: Roman Li <Roman.Li@amd.com>
:::::: CC: Alex Deucher <alexander.deucher@amd.com>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next reply other threads:[~2026-06-13 10:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-13 10:46 kernel test robot [this message]
-- strict thread matches above, loose matches on Subject: below --
2026-09-25 3:29 drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c:1114 dcn42_clk_mgr_construct() warn: inconsistent indenting kernel test robot
2026-09-29 20:03 kernel test robot
2026-10-02 18:14 kernel test robot
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