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[80.230.85.71]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-492202edc23sm177037195e9.2.2026.06.14.09.06.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Jun 2026 09:06:58 -0700 (PDT) Date: Sun, 14 Jun 2026 12:06:55 -0400 From: "Michael S. Tsirkin" To: Peter Maydell Cc: Richard Henderson , Gavin Shan , qemu-arm@nongnu.org, qemu-devel@nongnu.org, peterx@redhat.com, berrange@redhat.com, david@kernel.org, alex@shazbot.org, clg@redhat.com, pbonzini@redhat.com, philmd@mailo.com, phrdina@redhat.com, jugraham@redhat.com, shan.gavin@gmail.com Subject: Re: [PATCH 1/2] system/memory: Use __builtin_mem{cpy, move} in accessors of ram device region Message-ID: <20260614120334-mutt-send-email-mst@kernel.org> References: <20260612110307.1264798-1-gshan@redhat.com> <20260612110307.1264798-2-gshan@redhat.com> <223f5f94-b9b7-46b0-8466-5be655203a0e@linaro.org> <123d9e80-d731-42c7-81cc-71de47bb13d3@linaro.org> <20260614084004-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: FO41YLpVNwoK3nB3u4r7rCX2OyCm3qxkhIqxfLB0748_1781453220 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Sun, Jun 14, 2026 at 05:01:34PM +0100, Peter Maydell wrote: > On Sun, 14 Jun 2026 at 16:13, Michael S. Tsirkin wrote: > > > > On Fri, Jun 12, 2026 at 10:25:35AM -0700, Richard Henderson wrote: > > > On 6/12/26 09:36, Peter Maydell wrote: > > > > On Fri, 12 Jun 2026 at 16:29, Richard Henderson > > > > wrote: > > > > > > > > > > On 6/12/26 04:03, Gavin Shan wrote: > > > > > > This replaces mem{cpy, move} with __builtin_mem{cpy, move} in the memory > > > > > > accessors to ram device memory region, preparatory work to make ram device > > > > > > region directly accessible and bypass the bounce buffer in the DMA path > > > > > > in next patch. > > > > > > > > > > memcpy/memmove *always* compile to __builtin_memcpy/memmove, and the compiler later > > > > > decides whether or not to expand inline. > > > > > > > > Yes, but if you pass it a fixed small integer, then it is likely > > > > to expand it inline, whereas if you pass it a variable then it > > > > is likely not to... The patch is attempting to persuade the > > > > compiler to definitely do an inline access for 1, 2, 4, 8 > > > > byte access. > > > > > > Sure, for hosts with unaligned accesses. We still have sparc64 and (some?) > > > riscv64 that don't automatically have such and will compile to more than one > > > host instruction. > > > > > > > > My real question is: what are you attempting to achieve? > > > > > > > > > > (1) is the problem unaligned access to a mapped physical device? > > > > > (2) is the problem vector access to a mapped physical device? > > > > > (3) something else? > > > > > > > > I think there are two problems we're trying to fix here: > > > > > > > > (1) If a device does e.g. a pci_dma_write() with size 1, we want > > > > this to turn into exactly 1 byte write into guest memory, for the > > > > normal case where the guest memory is real host RAM. > > > > This deals with the e1000 bug where the pci_dma_write() turns into > > > > a call to glibc memmove() with size 1 and glibc's implementation > > > > turns that into 3 writes of the byte to the same address... > > > > > > Gotcha. Easily handled by not using memcpy/memmove at all. > > > > > > *(char *)ptr = val; > > > > > > is sufficient for all hosts. > > > > Yes, I think it does work because we use -fno-strict-aliasing. > > For bigger sizes we'll need packed because the addresses > > could be unaligned. > > IIRC "packed" will cause architectures that can't do > unaligned word accesses to emit code to do byte accesses, > so you don't want that. I mean, what's left to do if guest wants an unaligned access? Crash? On classical PCI, unaligned accesses are split up by the bus, so there's a decent chance most devices will be ok if qemu does it. > You need to explicitly check alignment, > I think. > > > But again, qemu simply already relies on this in bswap.h > > > > I kind of dislike muddying the waters by making several > > unrelated changes here. If we do we should change bwap too. > > The ldl_p etc functions in bswap.h provide different semantics: > ldl_p() is "do a load of a 32-bit quantity, even if the > address is not 4-aligned". We don't care if the compiler > or the memcpy ends up doing that as 4 byte accesses, which > on some hosts it must do. > > thanks > -- PMM I mean the ram device ops trick is using bounce buffers precisely because it happens to give you a single load. And yes on hosts where it does not work, these devices won't work, and qemu can't fix that. -- MST