[linux-next:master 9855/13763] drivers/gpu/drm/amd/amdgpu/../display/dc/dccg/dcn35/dcn35_dccg.c:512 dccg35_set_hdmistreamclk_rcg() warn: inconsistent indenting

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   c425609d6ac4012c8bbf01ec2e10e801b1923a7b
commit: d36771a03412454a0c7f1c81746426958008a2bb [9855/13763] drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRL
config: i386-randconfig-141-20260611 (https://download.01.org/0day-ci/archive/20260614/202606141620.rpa7SLtn-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
smatch: v0.5.0-9185-gbcc58b9c

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202606141620.rpa7SLtn-lkp@intel.com/

smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dccg/dcn35/dcn35_dccg.c:512 dccg35_set_hdmistreamclk_rcg() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dccg/dcn35/dcn35_dccg.c:534 dccg35_set_hdmi_char_clk_rcg() warn: inconsistent indenting

vim +512 drivers/gpu/drm/amd/amdgpu/../display/dc/dccg/dcn35/dcn35_dccg.c

   497	
   498	static void dccg35_set_hdmistreamclk_rcg(
   499			struct dccg *dccg,
   500			int inst,
   501			bool enable)
   502	{
   503		struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
   504	
   505		if (!dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream && enable)
   506			return;
   507	
   508		switch (inst) {
   509		case 0:
   510				REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, enable ? 0 : 1);
   511				REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, enable ? 0 : 1);
 > 512			break;
   513		default:
   514			BREAK_TO_DEBUGGER();
   515			return;
   516		}
   517	}
   518	
   519	static void dccg35_set_hdmi_char_clk_rcg(
   520			struct dccg *dccg,
   521			int inst,
   522			bool enable)
   523	{
   524		struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
   525	
   526		/* Only 1 HPO in DCN35 */
   527		if (!dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar && enable)
   528			return;
   529	
   530		switch (inst) {
   531		case 0:
   532				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, enable ? 0 : 1);
   533				REG_UPDATE(DCCG_GATE_DISABLE_CNTL4, HDMICHARCLK0_ROOT_GATE_DISABLE, enable ? 0 : 1);
 > 534			break;
   535		default:
   536			BREAK_TO_DEBUGGER();
   537			return;
   538		}
   539	}
   540	

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