From: Jisheng Zhang <jszhang@kernel.org>
To: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 4/5] spi: dw: use DW_SPI_INT_MASK instead of hardcoded 0xff
Date: Mon, 15 Jun 2026 12:40:38 +0800 [thread overview]
Message-ID: <20260615044039.9750-5-jszhang@kernel.org> (raw)
In-Reply-To: <20260615044039.9750-1-jszhang@kernel.org>
The Interrupt Mask Register valid bits is bit[5:0] which is well
defined with DW_SPI_INT_MASK, use it instead of the incorrect(but no
harm) and hardcoded 0xff.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
drivers/spi/spi-dw-core.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index aa2e51d0f959..feac17655847 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -228,7 +228,7 @@ static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
*/
dw_reader(dws);
if (!dws->rx_len) {
- dw_spi_mask_intr(dws, 0xff);
+ dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
spi_finalize_current_transfer(dws->ctlr);
} else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) {
dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1);
@@ -258,7 +258,7 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id)
return IRQ_NONE;
if (!ctlr->cur_msg) {
- dw_spi_mask_intr(dws, 0xff);
+ dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
return IRQ_HANDLED;
}
@@ -445,7 +445,7 @@ static int dw_spi_transfer_one(struct spi_controller *ctlr,
dws->dma_mapped = spi_xfer_is_dma_mapped(ctlr, spi, transfer);
/* For poll mode just disable all interrupts */
- dw_spi_mask_intr(dws, 0xff);
+ dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
if (dws->dma_mapped) {
ret = dws->dma_ops->dma_setup(dws, transfer);
@@ -704,7 +704,7 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
dw_spi_update_config(dws, mem->spi, &cfg);
- dw_spi_mask_intr(dws, 0xff);
+ dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
dw_spi_enable_chip(dws, 1);
--
2.53.0
next prev parent reply other threads:[~2026-06-15 5:00 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-15 4:40 [PATCH 0/5] spi: dw: use threaded interrupt Jisheng Zhang
2026-06-15 4:40 ` [PATCH 1/5] spi: dw: fix first spi transfer with dma always fallback to PIO Jisheng Zhang
2026-06-15 4:40 ` [PATCH 2/5] spi: dw: use the correct error msg if request_irq() fails Jisheng Zhang
2026-06-15 4:40 ` [PATCH 3/5] spi: dw: use DW_SPI_ISR directly Jisheng Zhang
2026-06-15 4:40 ` Jisheng Zhang [this message]
2026-06-15 4:40 ` [PATCH 5/5] spi: dw: use threaded interrupt and optimize the threaded ISR Jisheng Zhang
2026-06-15 5:37 ` Christophe JAILLET
2026-06-16 0:35 ` Jisheng Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260615044039.9750-5-jszhang@kernel.org \
--to=jszhang@kernel.org \
--cc=broonie@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.