From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D4F632BF52; Mon, 15 Jun 2026 12:38:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781527113; cv=none; b=M0EdoHLOevteRXwxBBoZLpGaEI5KvotR9cYLx+A4OKQz+rSMB679UgGAxoL6/E//BiaD4BxRixjyTro/GPosNxs4NFekzzhlDJEDsofA/la8u2C0ohzcuNqtqb2/evZ9pY/MzmxrD23mIKO1L2KH+KAeMO9qM5e3+ifmqpojpXw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781527113; c=relaxed/simple; bh=tzz0JSf1ZF0tUw8LwKVRiKptKJkeiPYuIws2VpU0R1Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=O58x3ndiqzWDXRylBP4VTb2W7rvTieyG1xLBiFMRma4+MMigKwNRxvLWZQqdL4bRyYu0IYMpjMuZcUZuWhS7R38+PfXpfvy62d41GE0VjVCkqQASpuS0VmuVmguQg/PwHODpyFxYmb0MNbb0D9hbrhf+slNtaFmHJ9iDdbLBnVo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=j3BmglUb; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="j3BmglUb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28BF01F000E9; Mon, 15 Jun 2026 12:38:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781527112; bh=INa7GhoaDabxSDGA5GIOXW3gtQQqTT3ikXo5/4MfYq0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=j3BmglUb18g/fkPeaFFodkzF5td/9xsvfn5SdWuF2utMETdx4GtCDlw+Uj5WhCrox plZjRQ+Slao5FoB3Gao+aJHnBI+50NfZe3q3ySWtOeqGpDnlR5+W6lMHHooQg8b3zm MC/t03gDaS4dHjO66Mb+SW2EjVtiNHW/LUVXsAqf5jg6S1WVnzTXZK500XeUuc9X/N XcvirrIjkEt29Ps/iql/ezNnrz4h9udC7rUqsmNVfYkn4VkGqbS4pmSNzyP5wzGcC6 X1r09qvFdtZwZig1+l1xUa4QhijVRdD7dqLmXgWaUm/M01jGfwCbjLCW41EaHuMI9y dKwBCX7CaIlcQ== From: Guo Ren To: zhangzhanpeng.jasper@bytedance.com Cc: alex@ghiti.fr, aou@eecs.berkeley.edu, cuiyunhui@bytedance.com, iommu@lists.linux.dev, joro@8bytes.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, luxu.kernel@bytedance.com, palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com, tjeznach@rivosinc.com, will@kernel.org, yuanzhu@bytedance.com Subject: Re: [PATCH v1] iommu/riscv: Support 32-bit register accesses Date: Mon, 15 Jun 2026 12:38:17 +0000 Message-ID: <20260615123821.373248-1-guoren@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260615064855.90316-1-zhangzhanpeng.jasper@bytedance.com> References: <20260615064855.90316-1-zhangzhanpeng.jasper@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Zhanpeng Zhang, I noticed you posted a similar fix recently. However, I had already submitted a similar solution back in September 2025 [1]. It would be great if you could review it. A few concerns with the current patch: 1. Using spin_lock_irqsave in such a small semantic structure is unnecessary. IRQ protection should be provided by the higher-level IOMMU driver interfaces. Many existing call sites already handle IRQ disabling, so adding it here feels redundant and adds avoidable overhead. 2. More critically, the RISCV_IOMMU_32BIT_ACCESS Kconfig option is problematic. According to the RISC-V IOMMU specification (Software Guidelines, “Reading and writing IOMMU registers”): > Registers that are 64-bit wide may be accessed using either a 32-bit > or a 64-bit access. This clearly requires that any hardware supporting 64-bit MMIO access must also support 32-bit MMIO access. Therefore, the IOMMU driver should be built on a 32-bit access base for maximum hardware compatibility. 3. Only performance-monitoring counters require 64-bit IO access or the high-low-high do-while retry strategy. For ordinary status and control MMIO registers, a single read is sufficient. 4. Introducing a compile-time Kconfig that forces 32-bit splitting (or 64-bit access) across the entire driver is unnecessary for the vast majority of registers and would prevent a single kernel Image (or .ko) from working across all compliant platforms. I believe the correct approach is to keep the driver on a 32-bit access foundation (as required by the spec) and apply special 64-bit or high-low-high handling only to performance-monitoring counters when justified by data. This preserves broad hardware support without unnecessary complexity. What do you think? I’m happy to discuss or collaborate on a cleaner solution based on the earlier patch [1]. [1]: https://lore.kernel.org/linux-riscv/20250903144217.837448-1-guoren@kernel.org/ Best Regards GUO Ren > Some RISC-V IOMMU implementations cannot perform 64-bit MMIO accesses > to the IOMMU register file. The RISC-V IOMMU architecture allows 64-bit > registers to be accessed using 32-bit accesses, provided the accesses are > properly aligned and do not span multiple registers. > > Add a config option for such implementations and access 64-bit IOMMU > registers as paired 32-bit MMIO operations when it is enabled. Serialize > the paired accesses so the high and low halves cannot interleave with > another CPU. Full 64-bit register programming writes the high half before > the low half. > > This option describes the register access width. It is not an RV32 kernel > mode and does not describe a 32-bit IOMMU architecture. > > Co-developed-by: Xu Lu > Signed-off-by: Xu Lu > Signed-off-by: Zhanpeng Zhang > --- > This is needed for platforms whose RISC-V IOMMU register window does not > support naturally aligned 64-bit MMIO accesses. > > drivers/iommu/riscv/Kconfig | 11 ++++++++ > drivers/iommu/riscv/iommu.c | 4 +++ > drivers/iommu/riscv/iommu.h | 55 +++++++++++++++++++++++++++++++++---- > 3 files changed, 64 insertions(+), 6 deletions(-) > > diff --git a/drivers/iommu/riscv/Kconfig b/drivers/iommu/riscv/Kconfig > index b86e5ab94183..54d624b9b2ef 100644 > --- a/drivers/iommu/riscv/Kconfig > +++ b/drivers/iommu/riscv/Kconfig > @@ -22,3 +22,14 @@ config RISCV_IOMMU_PCI > def_bool y if RISCV_IOMMU && PCI_MSI > help > Support for the PCIe implementation of RISC-V IOMMU architecture. > + > +config RISCV_IOMMU_32BIT_ACCESS > + bool "Use 32-bit accesses for RISC-V IOMMU registers" > + depends on RISCV_IOMMU > + help > + Say Y when the RISC-V IOMMU MMIO window cannot be accessed > + using naturally aligned 64-bit loads and stores. > + > + When enabled, 64-bit IOMMU registers are accessed as paired > + 32-bit MMIO operations. This option does not describe an RV32 > + kernel or a 32-bit IOMMU architecture. > diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c > index a31f50bbad35..7fa1721b5728 100644 > --- a/drivers/iommu/riscv/iommu.c > +++ b/drivers/iommu/riscv/iommu.c > @@ -53,6 +53,10 @@ struct riscv_iommu_devres { > void *addr; > }; > > +#ifdef CONFIG_RISCV_IOMMU_32BIT_ACCESS > +DEFINE_RAW_SPINLOCK(riscv_iommu_32bit_access_lock); > +#endif > + > static void riscv_iommu_devres_pages_release(struct device *dev, void *res) > { > struct riscv_iommu_devres *devres = res; > diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h > index 46df79dd5495..ba78ef1858c5 100644 > --- a/drivers/iommu/riscv/iommu.h > +++ b/drivers/iommu/riscv/iommu.h > @@ -14,6 +14,9 @@ > #include > #include > #include > +#ifdef CONFIG_RISCV_IOMMU_32BIT_ACCESS > +#include > +#endif > > #include "iommu-bits.h" > > @@ -69,21 +72,61 @@ void riscv_iommu_disable(struct riscv_iommu_device *iommu); > #define riscv_iommu_readl(iommu, addr) \ > readl_relaxed((iommu)->reg + (addr)) > > -#define riscv_iommu_readq(iommu, addr) \ > - readq_relaxed((iommu)->reg + (addr)) > - > #define riscv_iommu_writel(iommu, addr, val) \ > writel_relaxed((val), (iommu)->reg + (addr)) > > +#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ > + readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ > + delay_us, timeout_us) > + > +#ifndef CONFIG_RISCV_IOMMU_32BIT_ACCESS > +#define riscv_iommu_readq(iommu, addr) \ > + readq_relaxed((iommu)->reg + (addr)) > + > #define riscv_iommu_writeq(iommu, addr, val) \ > writeq_relaxed((val), (iommu)->reg + (addr)) > > #define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ > readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \ > delay_us, timeout_us) > +#else /* CONFIG_RISCV_IOMMU_32BIT_ACCESS */ > > -#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ > - readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ > - delay_us, timeout_us) > +extern raw_spinlock_t riscv_iommu_32bit_access_lock; > + > +static inline u64 __riscv_iommu_readq_relaxed(void __iomem *addr) > +{ > + u32 lo, hi; > + unsigned long flags; > + > + raw_spin_lock_irqsave(&riscv_iommu_32bit_access_lock, flags); > + do { > + hi = readl_relaxed(addr + sizeof(u32)); > + lo = readl_relaxed(addr); > + } while (hi != readl_relaxed(addr + sizeof(u32))); > + raw_spin_unlock_irqrestore(&riscv_iommu_32bit_access_lock, flags); > + > + return ((u64)hi << 32) | (u64)lo; > +} > + > +static inline void __riscv_iommu_writeq_relaxed(u64 value, void __iomem *addr) > +{ > + unsigned long flags; > + > + raw_spin_lock_irqsave(&riscv_iommu_32bit_access_lock, flags); > + writel_relaxed((u32)(value >> 32), addr + sizeof(u32)); > + writel_relaxed((u32)value, addr); > + raw_spin_unlock_irqrestore(&riscv_iommu_32bit_access_lock, flags); > +} > + > +#define riscv_iommu_readq(iommu, addr) \ > + __riscv_iommu_readq_relaxed((iommu)->reg + (addr)) > + > +#define riscv_iommu_writeq(iommu, addr, val) \ > + __riscv_iommu_writeq_relaxed((val), (iommu)->reg + (addr)) > + > +#define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \ > + readx_poll_timeout(__riscv_iommu_readq_relaxed, (iommu)->reg + (addr), \ > + val, cond, delay_us, timeout_us) > +#endif /* CONFIG_RISCV_IOMMU_32BIT_ACCESS */ > > #endif > -- > 2.50.1 (Apple Git-155) From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC1D8CD98C5 for ; Mon, 15 Jun 2026 12:38:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Wt/ChnWOFafJ3klag6j7KTWz3pa9ECLmVXw/t65t2gY=; b=F+D6pNGfFbKxLY g7wjgiZKKTSBvD/bM5bnFWqqSC6txNNtl7dQqsR6eOhTlbC9XVKj7z4DdAFxb/Su8Mi2U3HoidSBI R0lVqNVOlPdYo1r7NRujzrmKt787EZVY1fXaOktJPSDw/N6A7Tu7Lp4m3nSYtnS2CW0PpEJtL9mln ej9lQAdsWZuxEhKNpXX0ro8jgnelOp/tgtYFxxgBs3fECMlfOX/X/4DrdwIjj24W4EJ23CJzSrBkE l3xj8L0nNTTDlwR9WtX2vOCD5pQ7aaNUPqqvBH2Fp5I79B8fm4ptI+SnXYsExol5qvdv7Y8YMEq2C DyVVv3XtrEzIgbv4BA8w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wZ6aH-0000000EDaz-3Bxt; Mon, 15 Jun 2026 12:38:33 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wZ6aG-0000000EDai-44lZ for linux-riscv@lists.infradead.org; Mon, 15 Jun 2026 12:38:33 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 4CC9D4380A; Mon, 15 Jun 2026 12:38:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28BF01F000E9; Mon, 15 Jun 2026 12:38:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781527112; bh=INa7GhoaDabxSDGA5GIOXW3gtQQqTT3ikXo5/4MfYq0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=j3BmglUb18g/fkPeaFFodkzF5td/9xsvfn5SdWuF2utMETdx4GtCDlw+Uj5WhCrox plZjRQ+Slao5FoB3Gao+aJHnBI+50NfZe3q3ySWtOeqGpDnlR5+W6lMHHooQg8b3zm MC/t03gDaS4dHjO66Mb+SW2EjVtiNHW/LUVXsAqf5jg6S1WVnzTXZK500XeUuc9X/N XcvirrIjkEt29Ps/iql/ezNnrz4h9udC7rUqsmNVfYkn4VkGqbS4pmSNzyP5wzGcC6 X1r09qvFdtZwZig1+l1xUa4QhijVRdD7dqLmXgWaUm/M01jGfwCbjLCW41EaHuMI9y dKwBCX7CaIlcQ== From: Guo Ren To: zhangzhanpeng.jasper@bytedance.com Cc: alex@ghiti.fr, aou@eecs.berkeley.edu, cuiyunhui@bytedance.com, iommu@lists.linux.dev, joro@8bytes.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, luxu.kernel@bytedance.com, palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com, tjeznach@rivosinc.com, will@kernel.org, yuanzhu@bytedance.com Subject: Re: [PATCH v1] iommu/riscv: Support 32-bit register accesses Date: Mon, 15 Jun 2026 12:38:17 +0000 Message-ID: <20260615123821.373248-1-guoren@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260615064855.90316-1-zhangzhanpeng.jasper@bytedance.com> References: <20260615064855.90316-1-zhangzhanpeng.jasper@bytedance.com> MIME-Version: 1.0 X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SGkgWmhhbnBlbmcgWmhhbmcsCgpJIG5vdGljZWQgeW91IHBvc3RlZCBhIHNpbWlsYXIgZml4IHJl Y2VudGx5LiBIb3dldmVyLCBJIGhhZCBhbHJlYWR5CnN1Ym1pdHRlZCBhIHNpbWlsYXIgc29sdXRp b24gYmFjayBpbiBTZXB0ZW1iZXIgMjAyNSBbMV0uIEl0IHdvdWxkIGJlCmdyZWF0IGlmIHlvdSBj b3VsZCByZXZpZXcgaXQuIEEgZmV3IGNvbmNlcm5zIHdpdGggdGhlIGN1cnJlbnQgcGF0Y2g6Cgox LiBVc2luZyBzcGluX2xvY2tfaXJxc2F2ZSBpbiBzdWNoIGEgc21hbGwgc2VtYW50aWMgc3RydWN0 dXJlIGlzCnVubmVjZXNzYXJ5LiBJUlEgcHJvdGVjdGlvbiBzaG91bGQgYmUgcHJvdmlkZWQgYnkg dGhlIGhpZ2hlci1sZXZlbApJT01NVSBkcml2ZXIgaW50ZXJmYWNlcy4gTWFueSBleGlzdGluZyBj YWxsIHNpdGVzIGFscmVhZHkgaGFuZGxlIElSUQpkaXNhYmxpbmcsIHNvIGFkZGluZyBpdCBoZXJl IGZlZWxzIHJlZHVuZGFudCBhbmQgYWRkcyBhdm9pZGFibGUKb3ZlcmhlYWQuCgoyLiBNb3JlIGNy aXRpY2FsbHksIHRoZSBSSVNDVl9JT01NVV8zMkJJVF9BQ0NFU1MgS2NvbmZpZyBvcHRpb24gaXMK cHJvYmxlbWF0aWMuIEFjY29yZGluZyB0byB0aGUgUklTQy1WIElPTU1VIHNwZWNpZmljYXRpb24g KFNvZnR3YXJlCkd1aWRlbGluZXMsIOKAnFJlYWRpbmcgYW5kIHdyaXRpbmcgSU9NTVUgcmVnaXN0 ZXJz4oCdKToKCj4gUmVnaXN0ZXJzIHRoYXQgYXJlIDY0LWJpdCB3aWRlIG1heSBiZSBhY2Nlc3Nl ZCB1c2luZyBlaXRoZXIgYSAzMi1iaXQKPiBvciBhIDY0LWJpdCBhY2Nlc3MuCgpUaGlzIGNsZWFy bHkgcmVxdWlyZXMgdGhhdCBhbnkgaGFyZHdhcmUgc3VwcG9ydGluZyA2NC1iaXQgTU1JTyBhY2Nl c3MKbXVzdCBhbHNvIHN1cHBvcnQgMzItYml0IE1NSU8gYWNjZXNzLiBUaGVyZWZvcmUsIHRoZSBJ T01NVSBkcml2ZXIgc2hvdWxkCmJlIGJ1aWx0IG9uIGEgMzItYml0IGFjY2VzcyBiYXNlIGZvciBt YXhpbXVtIGhhcmR3YXJlIGNvbXBhdGliaWxpdHkuCgozLiBPbmx5IHBlcmZvcm1hbmNlLW1vbml0 b3JpbmcgY291bnRlcnMgcmVxdWlyZSA2NC1iaXQgSU8gYWNjZXNzIG9yIHRoZQpoaWdoLWxvdy1o aWdoIGRvLXdoaWxlIHJldHJ5IHN0cmF0ZWd5LiBGb3Igb3JkaW5hcnkgc3RhdHVzIGFuZCBjb250 cm9sCk1NSU8gcmVnaXN0ZXJzLCBhIHNpbmdsZSByZWFkIGlzIHN1ZmZpY2llbnQuCgo0LiBJbnRy b2R1Y2luZyBhIGNvbXBpbGUtdGltZSBLY29uZmlnIHRoYXQgZm9yY2VzIDMyLWJpdCBzcGxpdHRp bmcgKG9yCjY0LWJpdCBhY2Nlc3MpIGFjcm9zcyB0aGUgZW50aXJlIGRyaXZlciBpcyB1bm5lY2Vz c2FyeSBmb3IgdGhlIHZhc3QKbWFqb3JpdHkgb2YgcmVnaXN0ZXJzIGFuZCB3b3VsZCBwcmV2ZW50 IGEgc2luZ2xlIGtlcm5lbCBJbWFnZSAob3IgLmtvKQpmcm9tIHdvcmtpbmcgYWNyb3NzIGFsbCBj b21wbGlhbnQgcGxhdGZvcm1zLgoKSSBiZWxpZXZlIHRoZSBjb3JyZWN0IGFwcHJvYWNoIGlzIHRv IGtlZXAgdGhlIGRyaXZlciBvbiBhIDMyLWJpdCBhY2Nlc3MKZm91bmRhdGlvbiAoYXMgcmVxdWly ZWQgYnkgdGhlIHNwZWMpIGFuZCBhcHBseSBzcGVjaWFsIDY0LWJpdCBvcgpoaWdoLWxvdy1oaWdo IGhhbmRsaW5nIG9ubHkgdG8gcGVyZm9ybWFuY2UtbW9uaXRvcmluZyBjb3VudGVycyB3aGVuCmp1 c3RpZmllZCBieSBkYXRhLiBUaGlzIHByZXNlcnZlcyBicm9hZCBoYXJkd2FyZSBzdXBwb3J0IHdp dGhvdXQKdW5uZWNlc3NhcnkgY29tcGxleGl0eS4KCldoYXQgZG8geW91IHRoaW5rPyBJ4oCZbSBo YXBweSB0byBkaXNjdXNzIG9yIGNvbGxhYm9yYXRlIG9uIGEgY2xlYW5lcgpzb2x1dGlvbiBiYXNl ZCBvbiB0aGUgZWFybGllciBwYXRjaCBbMV0uCgpbMV06IGh0dHBzOi8vbG9yZS5rZXJuZWwub3Jn L2xpbnV4LXJpc2N2LzIwMjUwOTAzMTQ0MjE3LjgzNzQ0OC0xLWd1b3JlbkBrZXJuZWwub3JnLwoK QmVzdCBSZWdhcmRzCiAgR1VPIFJlbgoKPiBTb21lIFJJU0MtViBJT01NVSBpbXBsZW1lbnRhdGlv bnMgY2Fubm90IHBlcmZvcm0gNjQtYml0IE1NSU8gYWNjZXNzZXMKPiB0byB0aGUgSU9NTVUgcmVn aXN0ZXIgZmlsZS4gVGhlIFJJU0MtViBJT01NVSBhcmNoaXRlY3R1cmUgYWxsb3dzIDY0LWJpdAo+ IHJlZ2lzdGVycyB0byBiZSBhY2Nlc3NlZCB1c2luZyAzMi1iaXQgYWNjZXNzZXMsIHByb3ZpZGVk IHRoZSBhY2Nlc3NlcyBhcmUKPiBwcm9wZXJseSBhbGlnbmVkIGFuZCBkbyBub3Qgc3BhbiBtdWx0 aXBsZSByZWdpc3RlcnMuCj4gCj4gQWRkIGEgY29uZmlnIG9wdGlvbiBmb3Igc3VjaCBpbXBsZW1l bnRhdGlvbnMgYW5kIGFjY2VzcyA2NC1iaXQgSU9NTVUKPiByZWdpc3RlcnMgYXMgcGFpcmVkIDMy LWJpdCBNTUlPIG9wZXJhdGlvbnMgd2hlbiBpdCBpcyBlbmFibGVkLiBTZXJpYWxpemUKPiB0aGUg cGFpcmVkIGFjY2Vzc2VzIHNvIHRoZSBoaWdoIGFuZCBsb3cgaGFsdmVzIGNhbm5vdCBpbnRlcmxl YXZlIHdpdGgKPiBhbm90aGVyIENQVS4gRnVsbCA2NC1iaXQgcmVnaXN0ZXIgcHJvZ3JhbW1pbmcg d3JpdGVzIHRoZSBoaWdoIGhhbGYgYmVmb3JlCj4gdGhlIGxvdyBoYWxmLgo+IAo+IFRoaXMgb3B0 aW9uIGRlc2NyaWJlcyB0aGUgcmVnaXN0ZXIgYWNjZXNzIHdpZHRoLiBJdCBpcyBub3QgYW4gUlYz MiBrZXJuZWwKPiBtb2RlIGFuZCBkb2VzIG5vdCBkZXNjcmliZSBhIDMyLWJpdCBJT01NVSBhcmNo aXRlY3R1cmUuCj4gCj4gQ28tZGV2ZWxvcGVkLWJ5OiBYdSBMdSA8bHV4dS5rZXJuZWxAYnl0ZWRh bmNlLmNvbT4KPiBTaWduZWQtb2ZmLWJ5OiBYdSBMdSA8bHV4dS5rZXJuZWxAYnl0ZWRhbmNlLmNv bT4KPiBTaWduZWQtb2ZmLWJ5OiBaaGFucGVuZyBaaGFuZyA8emhhbmd6aGFucGVuZy5qYXNwZXJA Ynl0ZWRhbmNlLmNvbT4KPiAtLS0KPiBUaGlzIGlzIG5lZWRlZCBmb3IgcGxhdGZvcm1zIHdob3Nl IFJJU0MtViBJT01NVSByZWdpc3RlciB3aW5kb3cgZG9lcyBub3QKPiBzdXBwb3J0IG5hdHVyYWxs eSBhbGlnbmVkIDY0LWJpdCBNTUlPIGFjY2Vzc2VzLgo+IAo+ICBkcml2ZXJzL2lvbW11L3Jpc2N2 L0tjb25maWcgfCAxMSArKysrKysrKwo+ICBkcml2ZXJzL2lvbW11L3Jpc2N2L2lvbW11LmMgfCAg NCArKysKPiAgZHJpdmVycy9pb21tdS9yaXNjdi9pb21tdS5oIHwgNTUgKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrLS0tLQo+ICAzIGZpbGVzIGNoYW5nZWQsIDY0IGluc2VydGlvbnMo KyksIDYgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvaW9tbXUvcmlzY3Yv S2NvbmZpZyBiL2RyaXZlcnMvaW9tbXUvcmlzY3YvS2NvbmZpZwo+IGluZGV4IGI4NmU1YWI5NDE4 My4uNTRkNjI0YjliMmVmIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvaW9tbXUvcmlzY3YvS2NvbmZp Zwo+ICsrKyBiL2RyaXZlcnMvaW9tbXUvcmlzY3YvS2NvbmZpZwo+IEBAIC0yMiwzICsyMiwxNCBA QCBjb25maWcgUklTQ1ZfSU9NTVVfUENJCj4gIAlkZWZfYm9vbCB5IGlmIFJJU0NWX0lPTU1VICYm IFBDSV9NU0kKPiAgCWhlbHAKPiAgCSAgU3VwcG9ydCBmb3IgdGhlIFBDSWUgaW1wbGVtZW50YXRp b24gb2YgUklTQy1WIElPTU1VIGFyY2hpdGVjdHVyZS4KPiArCj4gK2NvbmZpZyBSSVNDVl9JT01N VV8zMkJJVF9BQ0NFU1MKPiArCWJvb2wgIlVzZSAzMi1iaXQgYWNjZXNzZXMgZm9yIFJJU0MtViBJ T01NVSByZWdpc3RlcnMiCj4gKwlkZXBlbmRzIG9uIFJJU0NWX0lPTU1VCj4gKwloZWxwCj4gKwkg IFNheSBZIHdoZW4gdGhlIFJJU0MtViBJT01NVSBNTUlPIHdpbmRvdyBjYW5ub3QgYmUgYWNjZXNz ZWQKPiArCSAgdXNpbmcgbmF0dXJhbGx5IGFsaWduZWQgNjQtYml0IGxvYWRzIGFuZCBzdG9yZXMu Cj4gKwo+ICsJICBXaGVuIGVuYWJsZWQsIDY0LWJpdCBJT01NVSByZWdpc3RlcnMgYXJlIGFjY2Vz c2VkIGFzIHBhaXJlZAo+ICsJICAzMi1iaXQgTU1JTyBvcGVyYXRpb25zLiBUaGlzIG9wdGlvbiBk b2VzIG5vdCBkZXNjcmliZSBhbiBSVjMyCj4gKwkgIGtlcm5lbCBvciBhIDMyLWJpdCBJT01NVSBh cmNoaXRlY3R1cmUuCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvaW9tbXUvcmlzY3YvaW9tbXUuYyBi L2RyaXZlcnMvaW9tbXUvcmlzY3YvaW9tbXUuYwo+IGluZGV4IGEzMWY1MGJiYWQzNS4uN2ZhMTcy MWI1NzI4IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvaW9tbXUvcmlzY3YvaW9tbXUuYwo+ICsrKyBi L2RyaXZlcnMvaW9tbXUvcmlzY3YvaW9tbXUuYwo+IEBAIC01Myw2ICs1MywxMCBAQCBzdHJ1Y3Qg cmlzY3ZfaW9tbXVfZGV2cmVzIHsKPiAgCXZvaWQgKmFkZHI7Cj4gIH07Cj4gIAo+ICsjaWZkZWYg Q09ORklHX1JJU0NWX0lPTU1VXzMyQklUX0FDQ0VTUwo+ICtERUZJTkVfUkFXX1NQSU5MT0NLKHJp c2N2X2lvbW11XzMyYml0X2FjY2Vzc19sb2NrKTsKPiArI2VuZGlmCj4gKwo+ICBzdGF0aWMgdm9p ZCByaXNjdl9pb21tdV9kZXZyZXNfcGFnZXNfcmVsZWFzZShzdHJ1Y3QgZGV2aWNlICpkZXYsIHZv aWQgKnJlcykKPiAgewo+ICAJc3RydWN0IHJpc2N2X2lvbW11X2RldnJlcyAqZGV2cmVzID0gcmVz Owo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2lvbW11L3Jpc2N2L2lvbW11LmggYi9kcml2ZXJzL2lv bW11L3Jpc2N2L2lvbW11LmgKPiBpbmRleCA0NmRmNzlkZDU0OTUuLmJhNzhlZjE4NThjNSAxMDA2 NDQKPiAtLS0gYS9kcml2ZXJzL2lvbW11L3Jpc2N2L2lvbW11LmgKPiArKysgYi9kcml2ZXJzL2lv bW11L3Jpc2N2L2lvbW11LmgKPiBAQCAtMTQsNiArMTQsOSBAQAo+ICAjaW5jbHVkZSA8bGludXgv aW9tbXUuaD4KPiAgI2luY2x1ZGUgPGxpbnV4L3R5cGVzLmg+Cj4gICNpbmNsdWRlIDxsaW51eC9p b3BvbGwuaD4KPiArI2lmZGVmIENPTkZJR19SSVNDVl9JT01NVV8zMkJJVF9BQ0NFU1MKPiArI2lu Y2x1ZGUgPGxpbnV4L3NwaW5sb2NrLmg+Cj4gKyNlbmRpZgo+ICAKPiAgI2luY2x1ZGUgImlvbW11 LWJpdHMuaCIKPiAgCj4gQEAgLTY5LDIxICs3Miw2MSBAQCB2b2lkIHJpc2N2X2lvbW11X2Rpc2Fi bGUoc3RydWN0IHJpc2N2X2lvbW11X2RldmljZSAqaW9tbXUpOwo+ICAjZGVmaW5lIHJpc2N2X2lv bW11X3JlYWRsKGlvbW11LCBhZGRyKSBcCj4gIAlyZWFkbF9yZWxheGVkKChpb21tdSktPnJlZyAr IChhZGRyKSkKPiAgCj4gLSNkZWZpbmUgcmlzY3ZfaW9tbXVfcmVhZHEoaW9tbXUsIGFkZHIpIFwK PiAtCXJlYWRxX3JlbGF4ZWQoKGlvbW11KS0+cmVnICsgKGFkZHIpKQo+IC0KPiAgI2RlZmluZSBy aXNjdl9pb21tdV93cml0ZWwoaW9tbXUsIGFkZHIsIHZhbCkgXAo+ICAJd3JpdGVsX3JlbGF4ZWQo KHZhbCksIChpb21tdSktPnJlZyArIChhZGRyKSkKPiAgCj4gKyNkZWZpbmUgcmlzY3ZfaW9tbXVf cmVhZGxfdGltZW91dChpb21tdSwgYWRkciwgdmFsLCBjb25kLCBkZWxheV91cywgdGltZW91dF91 cykgXAo+ICsJcmVhZHhfcG9sbF90aW1lb3V0KHJlYWRsX3JlbGF4ZWQsIChpb21tdSktPnJlZyAr IChhZGRyKSwgdmFsLCBjb25kLCBcCj4gKwkJCSAgIGRlbGF5X3VzLCB0aW1lb3V0X3VzKQo+ICsK PiArI2lmbmRlZiBDT05GSUdfUklTQ1ZfSU9NTVVfMzJCSVRfQUNDRVNTCj4gKyNkZWZpbmUgcmlz Y3ZfaW9tbXVfcmVhZHEoaW9tbXUsIGFkZHIpIFwKPiArCXJlYWRxX3JlbGF4ZWQoKGlvbW11KS0+ cmVnICsgKGFkZHIpKQo+ICsKPiAgI2RlZmluZSByaXNjdl9pb21tdV93cml0ZXEoaW9tbXUsIGFk ZHIsIHZhbCkgXAo+ICAJd3JpdGVxX3JlbGF4ZWQoKHZhbCksIChpb21tdSktPnJlZyArIChhZGRy KSkKPiAgCj4gICNkZWZpbmUgcmlzY3ZfaW9tbXVfcmVhZHFfdGltZW91dChpb21tdSwgYWRkciwg dmFsLCBjb25kLCBkZWxheV91cywgdGltZW91dF91cykgXAo+ICAJcmVhZHhfcG9sbF90aW1lb3V0 KHJlYWRxX3JlbGF4ZWQsIChpb21tdSktPnJlZyArIChhZGRyKSwgdmFsLCBjb25kLCBcCj4gIAkJ CSAgIGRlbGF5X3VzLCB0aW1lb3V0X3VzKQo+ICsjZWxzZSAvKiBDT05GSUdfUklTQ1ZfSU9NTVVf MzJCSVRfQUNDRVNTICovCj4gIAo+IC0jZGVmaW5lIHJpc2N2X2lvbW11X3JlYWRsX3RpbWVvdXQo aW9tbXUsIGFkZHIsIHZhbCwgY29uZCwgZGVsYXlfdXMsIHRpbWVvdXRfdXMpIFwKPiAtCXJlYWR4 X3BvbGxfdGltZW91dChyZWFkbF9yZWxheGVkLCAoaW9tbXUpLT5yZWcgKyAoYWRkciksIHZhbCwg Y29uZCwgXAo+IC0JCQkgICBkZWxheV91cywgdGltZW91dF91cykKPiArZXh0ZXJuIHJhd19zcGlu bG9ja190IHJpc2N2X2lvbW11XzMyYml0X2FjY2Vzc19sb2NrOwo+ICsKPiArc3RhdGljIGlubGlu ZSB1NjQgX19yaXNjdl9pb21tdV9yZWFkcV9yZWxheGVkKHZvaWQgX19pb21lbSAqYWRkcikKPiAr ewo+ICsJdTMyIGxvLCBoaTsKPiArCXVuc2lnbmVkIGxvbmcgZmxhZ3M7Cj4gKwo+ICsJcmF3X3Nw aW5fbG9ja19pcnFzYXZlKCZyaXNjdl9pb21tdV8zMmJpdF9hY2Nlc3NfbG9jaywgZmxhZ3MpOwo+ ICsJZG8gewo+ICsJCWhpID0gcmVhZGxfcmVsYXhlZChhZGRyICsgc2l6ZW9mKHUzMikpOwo+ICsJ CWxvID0gcmVhZGxfcmVsYXhlZChhZGRyKTsKPiArCX0gd2hpbGUgKGhpICE9IHJlYWRsX3JlbGF4 ZWQoYWRkciArIHNpemVvZih1MzIpKSk7Cj4gKwlyYXdfc3Bpbl91bmxvY2tfaXJxcmVzdG9yZSgm cmlzY3ZfaW9tbXVfMzJiaXRfYWNjZXNzX2xvY2ssIGZsYWdzKTsKPiArCj4gKwlyZXR1cm4gKCh1 NjQpaGkgPDwgMzIpIHwgKHU2NClsbzsKPiArfQo+ICsKPiArc3RhdGljIGlubGluZSB2b2lkIF9f cmlzY3ZfaW9tbXVfd3JpdGVxX3JlbGF4ZWQodTY0IHZhbHVlLCB2b2lkIF9faW9tZW0gKmFkZHIp Cj4gK3sKPiArCXVuc2lnbmVkIGxvbmcgZmxhZ3M7Cj4gKwo+ICsJcmF3X3NwaW5fbG9ja19pcnFz YXZlKCZyaXNjdl9pb21tdV8zMmJpdF9hY2Nlc3NfbG9jaywgZmxhZ3MpOwo+ICsJd3JpdGVsX3Jl bGF4ZWQoKHUzMikodmFsdWUgPj4gMzIpLCBhZGRyICsgc2l6ZW9mKHUzMikpOwo+ICsJd3JpdGVs X3JlbGF4ZWQoKHUzMil2YWx1ZSwgYWRkcik7Cj4gKwlyYXdfc3Bpbl91bmxvY2tfaXJxcmVzdG9y ZSgmcmlzY3ZfaW9tbXVfMzJiaXRfYWNjZXNzX2xvY2ssIGZsYWdzKTsKPiArfQo+ICsKPiArI2Rl ZmluZSByaXNjdl9pb21tdV9yZWFkcShpb21tdSwgYWRkcikgXAo+ICsJX19yaXNjdl9pb21tdV9y ZWFkcV9yZWxheGVkKChpb21tdSktPnJlZyArIChhZGRyKSkKPiArCj4gKyNkZWZpbmUgcmlzY3Zf aW9tbXVfd3JpdGVxKGlvbW11LCBhZGRyLCB2YWwpIFwKPiArCV9fcmlzY3ZfaW9tbXVfd3JpdGVx X3JlbGF4ZWQoKHZhbCksIChpb21tdSktPnJlZyArIChhZGRyKSkKPiArCj4gKyNkZWZpbmUgcmlz Y3ZfaW9tbXVfcmVhZHFfdGltZW91dChpb21tdSwgYWRkciwgdmFsLCBjb25kLCBkZWxheV91cywg dGltZW91dF91cykgXAo+ICsJcmVhZHhfcG9sbF90aW1lb3V0KF9fcmlzY3ZfaW9tbXVfcmVhZHFf cmVsYXhlZCwgKGlvbW11KS0+cmVnICsgKGFkZHIpLCBcCj4gKwkJCSAgIHZhbCwgY29uZCwgZGVs YXlfdXMsIHRpbWVvdXRfdXMpCj4gKyNlbmRpZiAvKiBDT05GSUdfUklTQ1ZfSU9NTVVfMzJCSVRf QUNDRVNTICovCj4gIAo+ICAjZW5kaWYKPiAtLSAKPiAyLjUwLjEgKEFwcGxlIEdpdC0xNTUpCgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1yaXNj diBtYWlsaW5nIGxpc3QKbGludXgtcmlzY3ZAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlz dHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJpc2N2Cg==