From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ABD43CC303; Tue, 16 Jun 2026 18:55:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781636156; cv=none; b=N0hpEh6LrnXCAFnApLWj7ZS0P06Ncry/+Eg1hr/TMOpYLX2aaFjfFJtOV5TlYlSws+V4pvS7hlA3IUma14LmaVul9oaYmpJDi9tDF4H0aIkYmHXBNSM7HKQwqdR5bq5N/RhxZfRi0gdhL2A+aG+ipx+su5eZTtKfEpkuNrXrZ60= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781636156; c=relaxed/simple; bh=TI2zK2qpnLnlgbqWQomMNmA2wp7Tn5blNcG3r7B1tyg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lVlPKyj4o1eZRwyDWwR0RMzlO2fJA+im+fJTwB2y/uVa7eTmz0TJjrXiDM391KUh9QRLOnLZxbSQ5uYk7UC/DvMyK9o7DQ8WPmRa55ODXNHBDefUPt1dtL8W6hxLNmpr6mlOUB/Ip/T49hueSmaG4hdPiHlPeoCXYXk/wJ7uVvk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=tHvHVMQ6; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="tHvHVMQ6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 303521F000E9; Tue, 16 Jun 2026 18:55:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1781636155; bh=PRNZjDVu/vrgB9yh57LLQrIceBUdwmUguia7YGU9l6o=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=tHvHVMQ6JrJ/pJnPmKM0Nb418NQSbzKV+bYdIthPt8W7mJ0SpZuJi1nTFutn8+DAB 4NgEjWAn3zBh1GJ/Bxj+Z8MIKaJJd6MD5rEZbuIx/8qYMO5yiUsrOM8XXerFUlNlYi poteLZL+13pfKhdKJNd8OudnsTYnv1fYaRx00Lww= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Zenghui Yu , Anshuman Khandual , Marc Zyngier , Mark Rutland , Will Deacon , Sasha Levin Subject: [PATCH 5.10 162/342] KVM: arm64: Remove VPIPT I-cache handling Date: Tue, 16 Jun 2026 20:27:38 +0530 Message-ID: <20260616145055.720009025@linuxfoundation.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260616145048.348037099@linuxfoundation.org> References: <20260616145048.348037099@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Marc Zyngier commit ced242ba9d7cb3571f6e0f165f643cb832d52148 upstream. We have some special handling for VPIPT I-cache in critical parts of the cache and TLB maintenance. Remove it. Reviewed-by: Zenghui Yu Reviewed-by: Anshuman Khandual Signed-off-by: Marc Zyngier Acked-by: Mark Rutland Link: https://lore.kernel.org/r/20231204143606.1806432-2-maz@kernel.org Signed-off-by: Will Deacon [Mark: Backport to v5.10.y. VPIPT HW was never built; this is all dead code] Signed-off-by: Mark Rutland Signed-off-by: Sasha Levin --- arch/arm64/include/asm/kvm_mmu.h | 4 ++-- arch/arm64/kvm/hyp/nvhe/tlb.c | 35 -------------------------------- arch/arm64/kvm/hyp/vhe/tlb.c | 13 ------------ 3 files changed, 2 insertions(+), 50 deletions(-) diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index 47dafd6ab3a30a..c700bf9241fce3 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -162,8 +162,8 @@ static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, if (icache_is_aliasing()) { /* any kind of VIPT cache */ __flush_icache_all(); - } else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) { - /* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */ + } else { + /* PIPT */ void *va = page_address(pfn_to_page(pfn)); invalidate_icache_range((unsigned long)va, diff --git a/arch/arm64/kvm/hyp/nvhe/tlb.c b/arch/arm64/kvm/hyp/nvhe/tlb.c index 229b06748c2084..435d0a54ab9a25 100644 --- a/arch/arm64/kvm/hyp/nvhe/tlb.c +++ b/arch/arm64/kvm/hyp/nvhe/tlb.c @@ -82,28 +82,6 @@ void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, dsb(ish); isb(); - /* - * If the host is running at EL1 and we have a VPIPT I-cache, - * then we must perform I-cache maintenance at EL2 in order for - * it to have an effect on the guest. Since the guest cannot hit - * I-cache lines allocated with a different VMID, we don't need - * to worry about junk out of guest reset (we nuke the I-cache on - * VMID rollover), but we do need to be careful when remapping - * executable pages for the same guest. This can happen when KSM - * takes a CoW fault on an executable page, copies the page into - * a page that was previously mapped in the guest and then needs - * to invalidate the guest view of the I-cache for that page - * from EL1. To solve this, we invalidate the entire I-cache when - * unmapping a page from a guest if we have a VPIPT I-cache but - * the host is running at EL1. As above, we could do better if - * we had the VA. - * - * The moral of this story is: if you have a VPIPT I-cache, then - * you should be running with VHE enabled. - */ - if (icache_is_vpipt()) - __flush_icache_all(); - __tlb_switch_to_host(&cxt); } @@ -142,18 +120,5 @@ void __kvm_flush_vm_context(void) { dsb(ishst); __tlbi(alle1is); - - /* - * VIPT and PIPT caches are not affected by VMID, so no maintenance - * is necessary across a VMID rollover. - * - * VPIPT caches constrain lookup and maintenance to the active VMID, - * so we need to invalidate lines with a stale VMID to avoid an ABA - * race after multiple rollovers. - * - */ - if (icache_is_vpipt()) - asm volatile("ic ialluis"); - dsb(ish); } diff --git a/arch/arm64/kvm/hyp/vhe/tlb.c b/arch/arm64/kvm/hyp/vhe/tlb.c index 66f17349f0c369..67047feb306876 100644 --- a/arch/arm64/kvm/hyp/vhe/tlb.c +++ b/arch/arm64/kvm/hyp/vhe/tlb.c @@ -146,18 +146,5 @@ void __kvm_flush_vm_context(void) { dsb(ishst); __tlbi(alle1is); - - /* - * VIPT and PIPT caches are not affected by VMID, so no maintenance - * is necessary across a VMID rollover. - * - * VPIPT caches constrain lookup and maintenance to the active VMID, - * so we need to invalidate lines with a stale VMID to avoid an ABA - * race after multiple rollovers. - * - */ - if (icache_is_vpipt()) - asm volatile("ic ialluis"); - dsb(ish); } -- 2.53.0