From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2FAD3DDDA1; Tue, 16 Jun 2026 19:08:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781636935; cv=none; b=ZvYLO5uD2j02aZ0MyEf7R1nnHDkyp9IHugfZWFc06D2RfIIRst5xugxVdKV5yvtq9xWJLyT3XD18aRykidt2hgpH7UwCO4VzEHlDAJBAiQtHySc78uIyyaSsdU7L92VdF5gdgL580pJcQ7WsBHBobh2HVtdro9KChsxwu5VwvR8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781636935; c=relaxed/simple; bh=nDCNN4hNFxbsFTZDoN1jBL4zpfF68E5Qt+QqD8vOSP8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T9x9HrL5LFsG/KrHvZiVQkvFD1ryTLInZoT4njLhQkSGZ3HQLOxzTlozM0LShK3bEfuEu2Moa81L7ZUViJcZyFhswIMOuMUR1aFchCJ/YGFpMRQ6n5zNblt4k8cxZ+8RQe4yl/jDrIvfN56kBJTIYxKMSIDissJlsn/NXPU/aoA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=piuH7FtX; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="piuH7FtX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA5401F000E9; Tue, 16 Jun 2026 19:08:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1781636934; bh=t+CF0Q+HhoNvmAHOGZGkPlYpyAo3TVGfR8MoPoWmp7Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=piuH7FtX8jbyAFZ3/kTzjg9Tw/Q1r/gH82tyBrr9HvZry36yD19t71y8AL2i56om+ FV/sQ2tD4ysQdvGy5BVEIV4FTYbPHOhpYn306i9JstwevDcg3q2nZdRovqv+DQn23a orPS+ViaUynZB96Wx2t2+N5nO0pyg5jij2dWOVm4= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Shanker Donthineni , Will Deacon , Mark Rutland Subject: [PATCH 5.10 334/342] arm64: cputype: Add NVIDIA Olympus definitions Date: Tue, 16 Jun 2026 20:30:30 +0530 Message-ID: <20260616145104.179524410@linuxfoundation.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260616145048.348037099@linuxfoundation.org> References: <20260616145048.348037099@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Shanker Donthineni commit e185c8a0d84236d14af61faff8147c953a878a77 upstream. Add cpu part and model macro definitions for NVIDIA Olympus core. Signed-off-by: Shanker Donthineni Signed-off-by: Will Deacon [Mark: backport to v5.10.y] Signed-off-by: Mark Rutland Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -121,6 +121,7 @@ #define NVIDIA_CPU_PART_DENVER 0x003 #define NVIDIA_CPU_PART_CARMEL 0x004 +#define NVIDIA_CPU_PART_OLYMPUS 0x010 #define FUJITSU_CPU_PART_A64FX 0x001 @@ -183,6 +184,7 @@ #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER) #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) +#define MIDR_NVIDIA_OLYMPUS MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_OLYMPUS) #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)