From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03F0135675A; Tue, 16 Jun 2026 17:04:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781629467; cv=none; b=q0zy0CxtdBAxHlowefW+Z4rYHMTESULqedTorO2jFMUSRwjnTpvzirR/MIYymz3GtssRrwX8cwx3e2xhVz8HG38u0kkL6BLVi1r3j5RkcY/LzkLTjW/BDaK5njl4gr7NTafMkktRyPGQvbZzN6fIFMNCS/ww0kzmAKdXBmyoP2s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781629467; c=relaxed/simple; bh=GGs/0Q/XlPvF/Mb5eVYWWFTBJPVw8w3/halRYVPca3A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TAjiyY8QZKXw+y/0nkGXLqIqOlqX/N6jZ79E8zuVmlwMgrD/S+QVADsmjGtF0sa+WaZEx9/TptgbjAUZJ6HpLgMLwn4OILvpqVWqxviKhziVYy+mLacD3okHkN5vat5eujQAOROS/eWa9EiqByJgkRjdg++hzSW3lyPL543JVnA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=0sc/UaYL; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="0sc/UaYL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E3A51F000E9; Tue, 16 Jun 2026 17:04:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1781629465; bh=9p0rmAQm512ccbEcNFA6igLibt2RRtFcYo0n/MMOAac=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=0sc/UaYLFuY94LZ/8Vn5ce7SOgWJVd5NsB+3oEI8kf05tByBl9x2TH1wIFHpUO2Bc l2xhDmLTwenoAcM4XbqXg3l0qyxZ7JNzQfEuJr9DUL18vC8kDMkLUeTXRvmt1G8m1N 9Kp097+WXTGQFYFwawZMWQ9o4suiyap22oUz2D7w= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ryan Roberts , Will Deacon , Sasha Levin Subject: [PATCH 6.6 257/452] arm64: tlb: Allow XZR argument to TLBI ops Date: Tue, 16 Jun 2026 20:28:04 +0530 Message-ID: <20260616145131.132661816@linuxfoundation.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260616145117.796205997@linuxfoundation.org> References: <20260616145117.796205997@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Mark Rutland commit bfd9c931d19aa59fb8371d557774fa169b15db9a upstream. The TLBI instruction accepts XZR as a register argument, and for TLBI operations with a register argument, there is no functional difference between using XZR or another GPR which contains zeroes. Operations without a register argument are encoded as if XZR were used. Allow the __TLBI_1() macro to use XZR when a register argument is all zeroes. Today this only results in a trivial code saving in __do_compat_cache_op()'s workaround for Neoverse-N1 erratum #1542419. In subsequent patches this pattern will be used more generally. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Catalin Marinas Cc: Marc Zyngier Cc: Oliver Upton Cc: Ryan Roberts Cc: Will Deacon Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Greg Kroah-Hartman [Mark: Backport to v6.6.y] Signed-off-by: Mark Rutland Signed-off-by: Sasha Levin --- arch/arm64/include/asm/tlbflush.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 6eeb56b6fac13e..c8d8b9622369f0 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -38,12 +38,12 @@ : : ) #define __TLBI_1(op, arg) asm (ARM64_ASM_PREAMBLE \ - "tlbi " #op ", %0\n" \ + "tlbi " #op ", %x0\n" \ ALTERNATIVE("nop\n nop", \ - "dsb ish\n tlbi " #op ", %0", \ + "dsb ish\n tlbi " #op ", %x0", \ ARM64_WORKAROUND_REPEAT_TLBI, \ CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ - : : "r" (arg)) + : : "rZ" (arg)) #define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg) -- 2.53.0