From: Stefan Hajnoczi <stefanha@redhat.com>
To: alistair23@gmail.com
Cc: qemu-devel@nongnu.org, alistair23@gmail.com,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 00/83] riscv-to-apply queue
Date: Tue, 16 Jun 2026 13:27:35 -0400 [thread overview]
Message-ID: <20260616172735.GA558674@fedora> (raw)
In-Reply-To: <20260616100527.1939565-1-alistair.francis@wdc.com>
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/11.1 for any user-visible changes.
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next prev parent reply other threads:[~2026-06-16 17:28 UTC|newest]
Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-16 10:04 [PULL 00/83] riscv-to-apply queue alistair23
2026-06-16 10:04 ` [PULL 01/83] target/riscv/tcg: disable svpbmt if satp_mode < sv39 alistair23
2026-06-16 10:04 ` [PULL 02/83] target/riscv: Align pmp size to pmp-granularity alistair23
2026-06-16 10:04 ` [PULL 03/83] target/riscv: Improve PMP address alignment readability alistair23
2026-06-16 10:04 ` [PULL 04/83] target/riscv/csr.c: do not allow mstatus MPV/GVA writes alistair23
2026-06-16 10:04 ` [PULL 05/83] target/riscv/csr.c: fix mstatus.UXL reserved value alistair23
2026-06-16 10:04 ` [PULL 06/83] disas/riscv.c: add 'cbo' insns to disassembler alistair23
2026-06-16 10:04 ` [PULL 07/83] target/riscv: Do not hide Sstc CSRs from gdbstub alistair23
2026-06-16 10:04 ` [PULL 08/83] target/riscv: Reject Svinval instructions in U-mode alistair23
2026-06-16 10:04 ` [PULL 09/83] target/riscv/insn_trans/trans_rvzicbo.c.inc: save opcode before helpers alistair23
2026-06-16 10:04 ` [PULL 10/83] target/riscv/cpu_helper.c: fault with reserved PTE.PBMT val alistair23
2026-06-16 10:04 ` [PULL 11/83] target/riscv/cpu_helper.c: allow LOAD_ADDR_MIS promotion to AMO fault alistair23
2026-06-16 10:04 ` [PULL 12/83] target/riscv: Fix size of gpr and gprh alistair23
2026-06-16 10:04 ` [PULL 13/83] target/riscv: Fix size of vector CSRs alistair23
2026-06-16 10:04 ` [PULL 14/83] target/riscv: Fix size of pc, load_[val|res] alistair23
2026-06-16 10:04 ` [PULL 15/83] target/riscv: Fix size of frm and fflags alistair23
2026-06-16 10:04 ` [PULL 16/83] target/riscv: Fix size of badaddr and bins alistair23
2026-06-16 10:04 ` [PULL 17/83] target/riscv: Fix size of guest_phys_fault_addr alistair23
2026-06-16 10:04 ` [PULL 18/83] target/riscv: Fix size of priv_ver and vext_ver alistair23
2026-06-16 10:04 ` [PULL 19/83] target/riscv: Fix size of retxh alistair23
2026-06-16 10:04 ` [PULL 20/83] target/riscv: Fix size of ssp alistair23
2026-06-16 10:04 ` [PULL 21/83] target/riscv: Fix size of excp_uw2 alistair23
2026-06-16 10:04 ` [PULL 22/83] target/riscv: Fix size of sw_check_code alistair23
2026-06-16 10:04 ` [PULL 23/83] target/riscv: Fix size of priv alistair23
2026-06-16 10:04 ` [PULL 24/83] target/riscv: Fix size of gei fields alistair23
2026-06-16 10:04 ` [PULL 25/83] target/riscv: Fix size of [m|s|vs]iselect fields alistair23
2026-06-16 10:04 ` [PULL 26/83] target/riscv: Fix arguments to board IMSIC emulation callbacks alistair23
2026-06-16 10:04 ` [PULL 27/83] target/riscv: Fix size of irq_overflow_left alistair23
2026-06-16 10:04 ` [PULL 28/83] target/riscv: Indent PMUFixedCtrState correctly alistair23
2026-06-16 10:04 ` [PULL 29/83] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() alistair23
2026-06-16 10:04 ` [PULL 30/83] target/riscv: Replace target_ulong in riscv_ctr_add_entry() alistair23
2026-06-16 10:04 ` [PULL 31/83] target/riscv: Fix size of trigger data alistair23
2026-06-16 10:04 ` [PULL 32/83] target/riscv: Fix size of mseccfg alistair23
2026-06-16 10:04 ` [PULL 33/83] target/riscv: Move debug.h include away from cpu.h alistair23
2026-06-16 10:04 ` [PULL 34/83] target/riscv: Move CSR declarations to separate csr.h header alistair23
2026-06-16 10:04 ` [PULL 35/83] target/riscv: Introduce externally facing CSR access functions alistair23
2026-06-16 10:04 ` [PULL 36/83] target/riscv: Make pmp.h target_ulong agnostic alistair23
2026-06-16 10:04 ` [PULL 37/83] target/riscv: Pass address as uint64_t in cpu_set_exception_base() alistair23
2026-06-16 10:04 ` [PULL 38/83] target/riscv: Fix pmp.h/cpu.h circular inclusion alistair23
2026-06-16 10:04 ` [PULL 39/83] target/riscv/cpu_helper.c: add PMA access fault alistair23
2026-06-16 10:04 ` [PULL 40/83] target/riscv/tcg: disable svnapot if satp_mode < sv39 alistair23
2026-06-16 10:04 ` [PULL 41/83] disas/riscv.c: fix inst_length() alistair23
2026-06-16 10:04 ` [PULL 42/83] target/riscv: Initialize DisasContext::mo_endian once alistair23
2026-06-16 10:04 ` [PULL 43/83] target/riscv: Implement runtime data endianness via MSTATUS bits alistair23
2026-06-16 10:04 ` [PULL 44/83] target/riscv: De-indent some code in get_physical_address() alistair23
2026-06-16 10:04 ` [PULL 45/83] target/riscv: Remove target_ulong use " alistair23
2026-06-16 10:04 ` [PULL 46/83] target/riscv: Fix page table walk endianness for big-endian harts alistair23
2026-06-16 10:04 ` [PULL 47/83] hw/riscv/boot: Rewrite setup_rom_reset_vec() using load/store API alistair23
2026-06-16 10:04 ` [PULL 48/83] hw/riscv/boot: Replace cpu_to_le32() -> const_le32() alistair23
2026-06-16 10:04 ` [PULL 49/83] target/riscv: Add big-endian CPU configuration field and reset logic alistair23
2026-06-16 10:04 ` [PULL 50/83] hw/riscv/boot: Honour data endianness alistair23
2026-06-16 10:04 ` [PULL 51/83] target/riscv: Expose and document the CPU 'big-endian' property alistair23
2026-06-16 10:04 ` [PULL 52/83] tests/functional: Add RISC-V endianness test alistair23
2026-06-16 10:04 ` [PULL 53/83] target/riscv: Add the implied rule for G extension alistair23
2026-06-16 10:04 ` [PULL 54/83] target/riscv: Add standard B extension implied rule alistair23
2026-06-16 10:04 ` [PULL 55/83] target/riscv: Print privilege level and ELP in riscv_cpu_dump_state alistair23
2026-06-16 10:04 ` [PULL 56/83] target/riscv: Improve alignment " alistair23
2026-06-16 10:05 ` [PULL 57/83] target/riscv: mask vxrm csrw write to the low 2 bits alistair23
2026-06-16 10:05 ` [PULL 58/83] target/riscv: Reorder Smrnmi CPU fields above CPU reset line alistair23
2026-06-16 10:05 ` [PULL 59/83] hw/riscv/numa.c: Supplement cpu topology arguments alistair23
2026-06-16 10:05 ` [PULL 60/83] hw/riscv: Don't insert DDT cache in Bare mode alistair23
2026-06-16 10:05 ` [PULL 61/83] hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling alistair23
2026-06-16 10:05 ` [PULL 62/83] hw/riscv/virt.c: fix 'iommu-map' FDT entry alistair23
2026-06-16 10:05 ` [PULL 63/83] target/riscv: Set mstatus.FS dirty when scalar FP raises exceptions alistair23
2026-06-16 10:05 ` [PULL 64/83] target/riscv: rvv: Set mstatus.FS dirty when vector " alistair23
2026-06-16 10:05 ` [PULL 65/83] disas/riscv: enable `mnret` disassembly alistair23
2026-06-16 10:05 ` [PULL 66/83] target/riscv: add thead-c908 cpu support alistair23
2026-06-16 10:05 ` [PULL 67/83] hw/riscv: add k230 board initial support alistair23
2026-06-16 10:05 ` [PULL 68/83] hw/watchdog: add k230 watchdog " alistair23
2026-06-16 10:05 ` [PULL 69/83] tests/qtest: add test for K230 watchdog alistair23
2026-06-16 10:05 ` [PULL 70/83] docs/system/riscv: add documentation for k230 machine alistair23
2026-06-16 10:05 ` [PULL 71/83] hw/riscv/sifive_u.c: add a FDT phandle to cpu-intc alistair23
2026-06-16 10:05 ` [PULL 72/83] hw/riscv: add fdt-common helper alistair23
2026-06-16 10:05 ` [PULL 73/83] hw/riscv/numa: make numa_enabled() public alistair23
2026-06-16 10:05 ` [PULL 74/83] hw/riscv: add create_fdt_socket_memory() helper alistair23
2026-06-16 10:05 ` [PULL 75/83] hw/riscv/sifive_u.c: add intc_phandles array alistair23
2026-06-16 10:05 ` [PULL 76/83] hw/riscv/spike.c: " alistair23
2026-06-16 10:05 ` [PULL 77/83] hw/riscv: add create_fdt_clint() helper alistair23
2026-06-16 10:05 ` [PULL 78/83] hw/riscv/sifive_u.c: add cpu-map, cluster and core DTs alistair23
2026-06-16 10:05 ` [PULL 79/83] hw/riscv: add fdt_create_cpu_socket_subnode() helper alistair23
2026-06-16 10:05 ` [PULL 80/83] hw/riscv: add create_fdt_socket_cpus() alistair23
2026-06-16 10:05 ` [PULL 81/83] hw/riscv/spike.c: use create_fdt_socket_cpus() alistair23
2026-06-16 10:05 ` [PULL 82/83] hw/riscv/fdt_common.c: create create_fdt_socket_cpu_internal() alistair23
2026-06-16 10:05 ` [PULL 83/83] hw/riscv: add create_fdt_socket_cpu_sifive() alistair23
2026-06-16 17:27 ` Stefan Hajnoczi [this message]
2026-06-16 19:49 ` [PULL 00/83] riscv-to-apply queue Michael Tokarev
2026-06-16 20:12 ` Daniel Henrique Barboza
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