From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by smtp.lore.kernel.org (Postfix) with ESMTP id 961A6CD98E6 for ; Wed, 17 Jun 2026 03:35:09 +0000 (UTC) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 08CB540E1E; Wed, 17 Jun 2026 05:34:43 +0200 (CEST) Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by mails.dpdk.org (Postfix) with ESMTP id 5F1A840A84; Wed, 17 Jun 2026 05:34:41 +0200 (CEST) X-QQ-mid: esmtpsz11t1781667279tb236cf21 X-QQ-Originating-IP: GbqbzPLjiS0zzz7sjA8AAoU1WBpfhN3JwJQwE+2OlZ0= Received: from DSK-zaiyuwang.trustnetic.com ( [183.157.22.210]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 17 Jun 2026 11:34:37 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 9957154874814321866 EX-QQ-RecipientCnt: 4 From: Zaiyu Wang To: dev@dpdk.org Cc: Zaiyu Wang , stable@dpdk.org, Jiawen Wu Subject: [PATCH v7 08/21] net/txgbe: fix link flow control registers for Amber-Lite Date: Wed, 17 Jun 2026 11:33:46 +0800 Message-Id: <20260617033400.376-9-zaiyuwang@trustnetic.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20260617033400.376-1-zaiyuwang@trustnetic.com> References: <20260423034024.14404-1-zaiyuwang@trustnetic.com> <20260617033400.376-1-zaiyuwang@trustnetic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: esmtpsz:trustnetic.com:qybglogicsvrsz:qybglogicsvrsz3b-0 X-QQ-XMAILINFO: NPtPVClv2hPaIvMz435kJeQee071O1dTb7jWGyejZ/RQ54ckSEw+Z7MJ Y5ohB5GYLKo9oUN68r62Cve1KCLtMJrpvloCTaHwsikpJ/7DfP+9mMbuZty5tvS4m36hInh FbXpgcA1YEtuoL1x+snVNMVUlCp8zRwr0WIYiq36PYAlrrzqLT0i+Qo/D3mPJ6sjKb1WIY+ KYV9cSBLFDbIOeLUVdtMcEI+tNcgCuHNR/FFMn/B9xynp7UjkTyTThSFwgeFROw1aILzszF CuFVsYNKtl0DPLV/LRcmdbZFL4B1i3C+XXuJHkT7uQpyGG1Lq6WKSX9HfkovidVdd3k/V8g agOM8sksQEFfKbLUiUWpjdH34EQvOA4DImqp2ywL5MOrNKqWmUxcewi6/hCHcFgzCGox3pv ao1250Wsx/pptLpMFLNaZz2t2RuIrQAGmuTWafM0XkcQUsydFl4R2LhMGulKGqTZet6Phqc zNcC4fEmSF63FOLXCRp1Y8VSjvv/XagrzuvbhEB+Rwr78ops1MqpY5NZbirUerD6paqsaHw +FwitZWZAPjD5wRP2l4iTZmwa4EhOGYV0gYwnMXnzFysKAIaNz+J1N2zLBeUvnCy0Xp2X+w pxLX/nLWAj63NCiKIUaLysEWzOzK4dbPrH7XY2Sl+UP24qrjc1A0SosU/WbRwmLZdDrkwUJ yPpTke02UWSAVvOhRJRozMkkqGmL5dHxABWbckFx6RJzqSAYiG0nUCq0aO7+AStm1KDlsv4 VEIrn/gf/oRgw3JNOb2Y9/6vX0OsV9/7oq6JxkSwYfDUDtkfDGnqrj99Ze0f6VIQZT9K/8e akgXzH+KEKBqVC/4Fw52XWu3Fzkshbb4D4qdMhA0OfWOvsA0zoALc1JC1z8kRTKt15tprc0 5TdbpZ6Jy9tIoKWUzUWzBW53I99gspeNCUaSYc7ITn2RgWFUNuLC9jZO580cKv6xIxcCdiR wbmFF2mCqI0Boelsy1B22leyafOKISHPh6y+HVIAMLjCmq84qBOVo0tp+fgODIpdBtKrK5J oWQ/D+CD1YCxuEKCZzU1uZ3XY+GsQdBaMU5GVavbvTKwYyYcie+mp+4cL7dQ1cklFdwHpOp QMH9XEIq2vG3Rxv/jksdJI= X-QQ-XMRINFO: Nq+8W0+stu50tPAe92KXseR0ZZmBTk3gLg== X-QQ-RECHKSPAM: 0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The flow control counter registers on AML NICs differ from those on SP NICs. Update the register offsets accordingly to ensure the counters work correctly. Fixes: fb6eb170dfa2 ("net/txgbe: add basic link configuration for Amber-Lite") Cc: stable@dpdk.org Signed-off-by: Zaiyu Wang --- drivers/net/txgbe/base/txgbe_hw.c | 7 ++++++ drivers/net/txgbe/base/txgbe_regs.h | 2 ++ drivers/net/txgbe/base/txgbe_type.h | 4 ++++ drivers/net/txgbe/txgbe_ethdev.c | 34 +++++++++++++++++++---------- 4 files changed, 36 insertions(+), 11 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 0f3db3a1ad..0d3310e15c 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -394,6 +394,13 @@ s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw) rd32(hw, TXGBE_PBTXLNKXON); rd32(hw, TXGBE_PBTXLNKXOFF); + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) { + wr32(hw, TXGBE_PBRXLNKXON_AML, 0); + wr32(hw, TXGBE_PBRXLNKXOFF_AML, 0); + hw->last_stats.rx_xon_packets = 0; + hw->last_stats.rx_xoff_packets = 0; + } + /* DMA Stats */ rd32(hw, TXGBE_DMARXPKT); rd32(hw, TXGBE_DMATXPKT); diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 3d1bc88430..22c46e3d56 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1085,6 +1085,8 @@ enum txgbe_5tuple_protocol { #define TXGBE_PBRXDROP 0x019068 #define TXGBE_PBRXLNKXOFF 0x011988 #define TXGBE_PBRXLNKXON 0x011E0C +#define TXGBE_PBRXLNKXOFF_AML 0x011F80 +#define TXGBE_PBRXLNKXON_AML 0x011F84 #define TXGBE_PBRXUPXON(up) (0x011E30 + (up) * 4) #define TXGBE_PBRXUPXOFF(up) (0x011E10 + (up) * 4) diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index ede780321f..505f598fb7 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -876,6 +876,10 @@ struct txgbe_hw { u64 tx_qp_bytes; u64 rx_qp_mc_packets; } qp_last[TXGBE_MAX_QP]; + struct { + u64 rx_xon_packets; + u64 rx_xoff_packets; + } last_stats; rte_spinlock_t phy_lock; /*amlite: new SW-FW mbox */ diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 099341b5ab..9b5a4b72e4 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -2264,16 +2264,18 @@ txgbe_dev_reset(struct rte_eth_dev *dev) return ret; } +#define TXGBE_UPDATE_COUNTER_32BIT_GENERIC(reg, last, count, reset) \ + do { \ + uint32_t current = rd32(hw, reg); \ + if ((current) < (last)) \ + current += 0x100000000ULL; \ + if (reset) \ + (last) = current; \ + (count) = (uint32_t)((current) - (last)); \ + } while (0) + #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \ - { \ - uint32_t current_counter = rd32(hw, reg); \ - if (current_counter < last_counter) \ - current_counter += 0x100000000LL; \ - if (!hw->offset_loaded) \ - last_counter = current_counter; \ - counter = current_counter - last_counter; \ - counter &= 0xFFFFFFFFLL; \ - } + TXGBE_UPDATE_COUNTER_32BIT_GENERIC(reg, last_counter, counter, !hw->offset_loaded) #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ { \ @@ -2331,8 +2333,18 @@ txgbe_read_stats_registers(struct txgbe_hw *hw, hw_stats->up[i].rx_up_dropped += rd32(hw, TXGBE_PBRXMISS(i)); } - hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON); - hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF); + + if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) { + TXGBE_UPDATE_COUNTER_32BIT_GENERIC(TXGBE_PBRXLNKXON_AML, + hw->last_stats.rx_xon_packets, + hw_stats->rx_xon_packets, !hw->offset_loaded); + TXGBE_UPDATE_COUNTER_32BIT_GENERIC(TXGBE_PBRXLNKXOFF_AML, + hw->last_stats.rx_xoff_packets, + hw_stats->rx_xoff_packets, !hw->offset_loaded); + } else { + hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON); + hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF); + } hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON); hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF); -- 2.21.0.windows.1