From: sashiko-bot@kernel.org
To: "Thierry Reding" <thierry.reding@kernel.org>
Cc: robh@kernel.org, devicetree@vger.kernel.org,
linux-pci@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v7 1/4] dt-bindings: pci: Strictly distinguish C0 from C1-C5
Date: Wed, 17 Jun 2026 20:25:26 +0000 [thread overview]
Message-ID: <20260617202526.7DA651F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260617-tegra264-pcie-v7-1-eae7ae964629@nvidia.com>
> From: Thierry Reding <treding@nvidia.com>
>
> Instead of using the ECAM registers as the first entry, strictly make a
> distinction between C0 and C1-C5. This is needed because otherwise the
> unit address doesn't match the first "reg" entry. We also cannot change
> the ordering of these nodes to follow the ECAM addresses because that
> would put them outside of their "control bus" hierarchy since the ECAM
> address space is a global one outside of any of the control busses.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260617-tegra264-pcie-v7-0-eae7ae964629@nvidia.com?part=1
next prev parent reply other threads:[~2026-06-17 20:25 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-17 16:01 [PATCH v7 0/4] PCI: tegra: Add Tegra264 support Thierry Reding
2026-06-17 16:01 ` [PATCH v7 1/4] dt-bindings: pci: Strictly distinguish C0 from C1-C5 Thierry Reding
2026-06-17 20:25 ` sashiko-bot [this message]
2026-06-17 16:01 ` [PATCH v7 2/4] PCI: Use standard wait times for PCIe link monitoring Thierry Reding
2026-06-17 20:40 ` sashiko-bot
2026-06-17 16:01 ` [PATCH v7 3/4] PCI: tegra: Add Tegra264 support Thierry Reding
2026-06-17 20:48 ` sashiko-bot
2026-06-17 16:01 ` [PATCH v7 4/4] arm64: tegra: Reorder reg and reg-names to match bindings Thierry Reding
2026-06-17 20:50 ` sashiko-bot
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