From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13920CD98F8 for ; Fri, 19 Jun 2026 08:23:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3EB3F10E070; Fri, 19 Jun 2026 08:23:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="gtGQWgwZ"; dkim-atps=neutral Received: from tor.source.kernel.org (tor.source.kernel.org [172.105.4.254]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8A4B910E066; Fri, 19 Jun 2026 08:23:20 +0000 (UTC) Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id A87CD601E1; Fri, 19 Jun 2026 08:23:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 986E11F000E9; Fri, 19 Jun 2026 08:23:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781857399; bh=L+9P1pLYmNIkJ1qDNJR3+PK+oN8UiZ+jU581/+pOwrM=; h=From:To:Cc:Subject:Date; b=gtGQWgwZQiXovLYg9u1Ev+CvpykmnKbyZqUL8wZXYW0d+IbRw6y5K29cYb7XBKlDm ztdBiDLc7gOj7EaQhGfQ9Wf4cduVHRVZpQJUKERRgi+hvN0fWR3i7UWemXKwTA3eF7 kw5E68WpJ0PUAR1s1UaY3UNRDpae4mNiG8dOqv6CJHdClXl7BbhrJc9f7aVAknVe4e +VItHqBDNvSlGp1gYy6byvXtd64D18q5vS+TG1qDzTH1RVLqfJH7sMsqSEHnsnsH1T dH+exfg/CqpLr8Y+1IOjY/QD9vbaVt10Qc/D4OSS31oFr6/HbImOaRuUFgqp+CIdfg gIkf0LFJIjGUw== From: Arnd Bergmann To: Harry Wentland , Leo Li , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Simona Vetter , Ovidiu Bunea , Ray Wu , Leo Chen Cc: Arnd Bergmann , Rodrigo Siqueira , Gaghik Khachatrian , Dillon Varone , Chuanyu Tseng , Linus Probert , Kees Cook , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/amd/display: avoid 64-bit division Date: Fri, 19 Jun 2026 10:23:00 +0200 Message-Id: <20260619082313.3583603-1-arnd@kernel.org> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Arnd Bergmann 64-bit division is costly on 32-bit targets and should be avoided: x86_64-linux-ld: drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.o: in function `get_dp_dto_frequency_100hz': dce_clock_source.c:(.text+0x407): undefined reference to `__udivdi3' x86_64-linux-ld: drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.o: in function `dcn401_get_dp_dto_frequency_100hz': dce_clock_source.c:(.text+0x8b8): undefined reference to `__udivdi3' Replace the open-coded division with a div_u64() call where necessary. This could be done in a more clever way using mul_u64_u32_shr() or similar, but since this is called rarely, use the most readable variant that works. Fixes: 6f6483dbfacd ("drm/amd/display: Update get_pixel_clk_frequency() for DCN4x DCCG DP DTO") Signed-off-by: Arnd Bergmann --- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 7c293917e6fd..501ab1a3bac2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1229,9 +1229,9 @@ static bool get_dp_dto_frequency_100hz( */ modulo_hz = REG_READ(MODULO[inst]); if (modulo_hz) { - temp = div_u64((uint64_t)clock_hz * dp_dto_ref_khz * 10, modulo_hz); - ASSERT(temp / 100 <= 0xFFFFFFFFUL); - *pixel_clk_100hz = (unsigned int)(temp / 100); + temp = clock_hz * dp_dto_ref_khz * 10; + ASSERT(temp <= INT_MAX * modulo_hz * 100); + *pixel_clk_100hz = div_u64(temp, modulo_hz * 100); } else *pixel_clk_100hz = 0; } else { @@ -1286,12 +1286,12 @@ static bool dcn401_get_dp_dto_frequency_100hz(const struct clock_source *clock_s */ temp = (unsigned long long)dp_dto_integer * modulo_hz + phase_hz; - if (temp / 100 > 0xFFFFFFFFUL) { + if (temp > (UINT_MAX * 100ULL)) { /* pixel rate 100hz should never be this high, if it is, throw an assert and return 0 */ BREAK_TO_DEBUGGER(); *pixel_clk_100hz = 0; } else { - *pixel_clk_100hz = (unsigned int)(temp / 100); + *pixel_clk_100hz = div_u64(temp, 100); } return true; -- 2.39.5