From: sashiko-bot@kernel.org
To: "Drew Fustini" <fustini@kernel.org>
Cc: linux-rt-devel@lists.linux.dev, devicetree@vger.kernel.org,
conor+dt@kernel.org, linux-kernel@vger.kernel.org,
robh@kernel.org
Subject: Re: [PATCH 8/8] riscv_cbqri: Add CBQRI cache capacity-allocation platform driver
Date: Fri, 19 Jun 2026 18:41:04 +0000 [thread overview]
Message-ID: <20260619184104.F1C4C1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260619-dfustini-atl-sc-cbqri-dt-v1-8-e79a7723fab0@kernel.org>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [High] `get_cpu_cacheinfo_level()` fails to discover capacity controllers on split caches.
Pre-existing issues:
- [High] Global list `cbqri_controllers` is modified concurrently without a lock.
--
commit a409dc1e72a5139a209d981205820cfe3a0eb512
Author: Drew Fustini <fustini@kernel.org>
riscv_cbqri: Add CBQRI cache capacity-allocation platform driver
The CBQRI core exposes riscv_cbqri_register_cc_dt() so a device-tree
platform driver can register a capacity controller whose cache topology
it already knows.
> diff --git a/drivers/resctrl/cbqri_capacity.c b/drivers/resctrl/cbqri_capacity.c
> new file mode 100644
> index 0000000000000..2172432eb3287
> --- /dev/null
> +++ b/drivers/resctrl/cbqri_capacity.c
[ ... ]
> + /*
> + * Associate the controller with its cache instance via
> + * cacheinfo. The matching cache provides the cache id and the
> + * set of harts that share the cache.
> + */
> + cache_id = -1;
> + cpus_read_lock();
> + for_each_online_cpu(cpu) {
> + struct cacheinfo *ci = get_cpu_cacheinfo_level(cpu, cache_level);
> +
> + if (ci && ci->fw_token == cache_np) {
> + cache_id = ci->id;
> + cpumask_copy(cpu_mask, &ci->shared_cpu_map);
> + break;
> + }
> + }
> + cpus_read_unlock();
[Severity: High]
Will this fail to discover capacity controllers on split caches?
get_cpu_cacheinfo_level() only returns the first cache leaf that matches
the requested level and stops searching. If a CPU has multiple caches at
the same level (e.g., split L1 Instruction and L1 Data caches), and the
capacity controller governs the second one, get_cpu_cacheinfo_level() will
return the first cache. Its fw_token will not match cache_np.
Consequently, the loop will never find the matching cache, cache_id will
remain -1, and the probe will incorrectly fail with -ENODEV.
[ ... ]
> + info.type = CBQRI_CONTROLLER_TYPE_CAPACITY;
> + info.addr = res->start;
> + info.size = resource_size(res);
> + info.rcid_count = rcid_count;
> + info.cache_id = cache_id;
> +
> + ret = riscv_cbqri_register_cc_dt(&info, cache_level, cpu_mask);
> + if (ret) {
> + dev_err(dev, "failed to register capacity controller: %d\n", ret);
> + goto out_free;
> + }
[Severity: High]
This is a pre-existing issue, but can this trigger list corruption if
multiple instances of the platform driver probe concurrently?
The probe function cbqri_capacity_probe() calls
riscv_cbqri_register_cc_dt(). Inside riscv_cbqri_register_cc_dt(), the newly
allocated controller is appended to the global cbqri_controllers list:
riscv_cbqri_register_cc_dt() {
...
list_add_tail(&ctrl->list, &cbqri_controllers);
return 0;
}
This modification happens without any locks. If the driver core probes
multiple CBQRI devices concurrently (e.g., due to asynchronous probing),
list_add_tail() will race on the shared list. Additionally, an asynchronous
probe could race with CPU hotplug events iterating over cbqri_controllers.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260619-dfustini-atl-sc-cbqri-dt-v1-0-e79a7723fab0@kernel.org?part=8
prev parent reply other threads:[~2026-06-19 18:41 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-19 18:29 [PATCH 0/8] riscv: Add Ssqosid and initial CBQRI resctrl support Drew Fustini
2026-06-19 18:29 ` Drew Fustini
2026-06-19 18:29 ` [PATCH 1/8] dt-bindings: riscv: Add Ssqosid extension description Drew Fustini
2026-06-19 18:29 ` Drew Fustini
2026-06-19 18:29 ` [PATCH 2/8] riscv: Detect the Ssqosid extension Drew Fustini
2026-06-19 18:29 ` Drew Fustini
2026-06-19 18:29 ` [PATCH 3/8] riscv: Add support for srmcfg CSR from " Drew Fustini
2026-06-19 18:29 ` Drew Fustini
2026-06-19 18:40 ` sashiko-bot
2026-06-19 18:29 ` [PATCH 4/8] riscv_cbqri: Add capacity controller probe and allocation device ops Drew Fustini
2026-06-19 18:29 ` Drew Fustini
2026-06-19 18:40 ` sashiko-bot
2026-06-19 18:29 ` [PATCH 5/8] riscv_cbqri: resctrl: Add cache allocation via capacity block mask Drew Fustini
2026-06-19 18:29 ` Drew Fustini
2026-06-19 18:42 ` sashiko-bot
2026-06-19 18:29 ` [PATCH 6/8] riscv: Enable resctrl filesystem for Ssqosid Drew Fustini
2026-06-19 18:29 ` Drew Fustini
2026-06-19 18:45 ` sashiko-bot
2026-06-19 18:29 ` [PATCH 7/8] dt-bindings: riscv: Add generic CBQRI controller binding Drew Fustini
2026-06-19 18:29 ` Drew Fustini
2026-06-19 18:29 ` [PATCH 8/8] riscv_cbqri: Add CBQRI cache capacity-allocation platform driver Drew Fustini
2026-06-19 18:29 ` Drew Fustini
2026-06-19 18:41 ` sashiko-bot [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260619184104.F1C4C1F000E9@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=fustini@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-rt-devel@lists.linux.dev \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.