From: Borislav Petkov <bp@kernel.org>
To: X86 ML <x86@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
"Borislav Petkov (AMD)" <bp@alien8.de>
Subject: [PATCH] x86/cpu: Hide and rename static_cpu_has()
Date: Fri, 19 Jun 2026 18:50:41 -0700 [thread overview]
Message-ID: <20260620015041.336288-1-bp@kernel.org> (raw)
From: "Borislav Petkov (AMD)" <bp@alien8.de>
cpu_feature_enabled() is the one to use to test feature flags so hide
the static thing which doesn't pay attention to disabled mask bits
anyway.
Use the following command to do the replacement:
$ git grep --files-with-matches -w static_cpu_has -- ':(exclude)*cpufeature.h' \
| xargs sed -i 's/static_cpu_has(/cpu_feature_enabled\(/g'
There should be no functional changes resulting from this.
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
---
arch/um/include/asm/cpufeature.h | 16 +++---------
arch/x86/events/amd/core.c | 2 +-
arch/x86/events/intel/core.c | 2 +-
arch/x86/events/intel/lbr.c | 26 +++++++++----------
arch/x86/events/perf_event.h | 2 +-
arch/x86/include/asm/archrandom.h | 4 +--
arch/x86/include/asm/cpufeature.h | 10 +++----
arch/x86/include/asm/debugreg.h | 2 +-
arch/x86/include/asm/pgtable.h | 4 +--
arch/x86/include/asm/sync_core.h | 4 +--
arch/x86/kernel/apic/apic_numachip.c | 2 +-
arch/x86/kernel/cpu/bugs.c | 10 +++----
arch/x86/kernel/cpu/cacheinfo.c | 2 +-
arch/x86/kernel/fpu/core.c | 2 +-
arch/x86/kernel/fpu/signal.c | 2 +-
arch/x86/kernel/kprobes/opt.c | 2 +-
arch/x86/kernel/ldt.c | 2 +-
arch/x86/kernel/process.c | 10 +++----
arch/x86/kernel/process_64.c | 6 ++---
arch/x86/kernel/signal_32.c | 2 +-
arch/x86/kernel/time.c | 2 +-
arch/x86/kernel/vmlinux.lds.S | 2 +-
arch/x86/kvm/cpuid.c | 4 +--
arch/x86/kvm/svm/svm.c | 22 ++++++++--------
arch/x86/kvm/vmx/vmx.c | 6 ++---
arch/x86/kvm/x86.c | 6 ++---
arch/x86/kvm/xen.c | 2 +-
arch/x86/lib/copy_mc.c | 4 +--
arch/x86/lib/usercopy_32.c | 2 +-
arch/x86/mm/extable.c | 2 +-
arch/x86/mm/pat/set_memory.c | 2 +-
arch/x86/mm/tlb.c | 14 +++++-----
drivers/firewire/ohci.c | 2 +-
drivers/gpu/drm/drm_cache.c | 8 +++---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 4 +--
drivers/gpu/drm/i915/i915_memcpy.c | 2 +-
drivers/md/dm-writecache.c | 2 +-
.../intel/speed_select_if/isst_tpmi_core.c | 2 +-
drivers/thermal/intel/therm_throt.c | 2 +-
39 files changed, 97 insertions(+), 105 deletions(-)
diff --git a/arch/um/include/asm/cpufeature.h b/arch/um/include/asm/cpufeature.h
index 4354f6984271..f7770083c0a4 100644
--- a/arch/um/include/asm/cpufeature.h
+++ b/arch/um/include/asm/cpufeature.h
@@ -49,7 +49,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
* is not relevant.
*/
#define cpu_feature_enabled(bit) \
- (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit))
+ (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : _static_cpu_has(bit))
#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
@@ -64,15 +64,7 @@ extern void setup_clear_cpu_cap(unsigned int bit);
#define setup_force_cpu_bug(bit) setup_force_cpu_cap(bit)
-/*
- * Static testing of CPU features. Used the same as boot_cpu_has(). It
- * statically patches the target code for additional performance. Use
- * static_cpu_has() only in fast paths, where every cycle counts. Which
- * means that the boot_cpu_has() variant is already fast enough for the
- * majority of cases and you should stick to using it as it is generally
- * only two instructions: a RIP-relative MOV and a TEST.
- */
-static __always_inline bool _static_cpu_has(u16 bit)
+static __always_inline bool __static_cpu_has(u16 bit)
{
asm goto("1: jmp 6f\n"
"2:\n"
@@ -116,7 +108,7 @@ static __always_inline bool _static_cpu_has(u16 bit)
return false;
}
-#define static_cpu_has(bit) \
+#define _static_cpu_has(bit) \
( \
__builtin_constant_p(boot_cpu_has(bit)) ? \
boot_cpu_has(bit) : \
@@ -126,7 +118,7 @@ static __always_inline bool _static_cpu_has(u16 bit)
#define cpu_has_bug(c, bit) cpu_has(c, (bit))
#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit))
-#define static_cpu_has_bug(bit) static_cpu_has((bit))
+#define static_cpu_has_bug(bit) _static_cpu_has((bit))
#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit))
#define boot_cpu_set_bug(bit) set_cpu_cap(&boot_cpu_data, (bit))
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 6569048a8c1c..11f499cc2dc3 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -1388,7 +1388,7 @@ static struct attribute *amd_brs_events_attrs[] = {
static umode_t
amd_brs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
{
- return static_cpu_has(X86_FEATURE_BRS) && x86_pmu.lbr_nr ?
+ return cpu_feature_enabled(X86_FEATURE_BRS) && x86_pmu.lbr_nr ?
attr->mode : 0;
}
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2b35483e2b70..153f29ecb217 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6360,7 +6360,7 @@ static void intel_pmu_cpu_starting(int cpu)
* Deal with CPUs that don't clear their LBRs on power-up, and that may
* even boot with LBRs enabled.
*/
- if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr)
+ if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr)
msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT);
intel_pmu_lbr_reset();
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index cae2e02fe6cc..55c3b2fcb904 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -109,7 +109,7 @@ static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
static __always_inline bool is_lbr_call_stack_bit_set(u64 config)
{
- if (static_cpu_has(X86_FEATURE_ARCH_LBR))
+ if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
return !!(config & ARCH_LBR_CALL_STACK);
return !!(config & LBR_CALL_STACK);
@@ -138,13 +138,13 @@ static void __intel_pmu_lbr_enable(bool pmi)
*/
if (cpuc->lbr_sel)
lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
- if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && !pmi && cpuc->lbr_sel)
+ if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && !pmi && cpuc->lbr_sel)
wrmsrq(MSR_LBR_SELECT, lbr_select);
rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
orig_debugctl = debugctl;
- if (!static_cpu_has(X86_FEATURE_ARCH_LBR))
+ if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
debugctl |= DEBUGCTLMSR_LBR;
/*
* LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
@@ -159,7 +159,7 @@ static void __intel_pmu_lbr_enable(bool pmi)
if (orig_debugctl != debugctl)
wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
- if (static_cpu_has(X86_FEATURE_ARCH_LBR))
+ if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
wrmsrq(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN);
}
@@ -200,7 +200,7 @@ void intel_pmu_lbr_reset(void)
cpuc->last_task_ctx = NULL;
cpuc->last_log_id = 0;
- if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && cpuc->lbr_select)
+ if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && cpuc->lbr_select)
wrmsrq(MSR_LBR_SELECT, 0);
}
@@ -418,7 +418,7 @@ static void intel_pmu_arch_lbr_xrstors(void *ctx)
static __always_inline bool lbr_is_reset_in_cstate(void *ctx)
{
- if (static_cpu_has(X86_FEATURE_ARCH_LBR))
+ if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
return x86_pmu.lbr_deep_c_reset && !rdlbr_from(0, NULL);
return !rdlbr_from(((struct x86_perf_task_context *)ctx)->tos, NULL);
@@ -624,7 +624,7 @@ void release_lbr_buffers(void)
struct cpu_hw_events *cpuc;
int cpu;
- if (!static_cpu_has(X86_FEATURE_ARCH_LBR))
+ if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
return;
for_each_possible_cpu(cpu) {
@@ -643,7 +643,7 @@ void reserve_lbr_buffers(void)
struct cpu_hw_events *cpuc;
int cpu;
- if (!static_cpu_has(X86_FEATURE_ARCH_LBR))
+ if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
return;
for_each_possible_cpu(cpu) {
@@ -730,7 +730,7 @@ void intel_pmu_lbr_disable_all(void)
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
if (cpuc->lbr_users && !vlbr_exclude_host()) {
- if (static_cpu_has(X86_FEATURE_ARCH_LBR))
+ if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
return __intel_pmu_arch_lbr_disable();
__intel_pmu_lbr_disable();
@@ -889,7 +889,7 @@ static __always_inline u16 get_lbr_cycles(u64 info)
{
u16 cycles = info & LBR_INFO_CYCLES;
- if (static_cpu_has(X86_FEATURE_ARCH_LBR) &&
+ if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR) &&
(!static_branch_likely(&x86_lbr_cycles) ||
!(info & LBR_INFO_CYC_CNT_VALID)))
cycles = 0;
@@ -1124,7 +1124,7 @@ static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
reg = &event->hw.branch_reg;
reg->idx = EXTRA_REG_LBR;
- if (static_cpu_has(X86_FEATURE_ARCH_LBR)) {
+ if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR)) {
reg->config = mask;
/*
@@ -1232,7 +1232,7 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
* Doesn't support OTHER_BRANCH decoding for now.
* OTHER_BRANCH branch type still rely on software decoding.
*/
- if (static_cpu_has(X86_FEATURE_ARCH_LBR) &&
+ if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR) &&
type <= ARCH_LBR_BR_TYPE_KNOWN_MAX) {
to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
type = arch_lbr_br_type_map[type] | to_plm;
@@ -1279,7 +1279,7 @@ void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr)
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
/* Cannot get TOS for large PEBS and Arch LBR */
- if (static_cpu_has(X86_FEATURE_ARCH_LBR) ||
+ if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR) ||
(cpuc->n_pebs == cpuc->n_large_pebs))
cpuc->lbr_stack.hw_idx = -1ULL;
else
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index eae24bb35dc1..a91ed27f026b 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1175,7 +1175,7 @@ DECLARE_STATIC_CALL(x86_pmu_pebs_disable_all, *x86_pmu.pebs_disable_all);
static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
{
- if (static_cpu_has(X86_FEATURE_ARCH_LBR))
+ if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt;
return &((struct x86_perf_task_context *)ctx)->opt;
diff --git a/arch/x86/include/asm/archrandom.h b/arch/x86/include/asm/archrandom.h
index 4c305305871b..cb1f1e15a0b9 100644
--- a/arch/x86/include/asm/archrandom.h
+++ b/arch/x86/include/asm/archrandom.h
@@ -45,12 +45,12 @@ static inline bool __must_check rdseed_long(unsigned long *v)
static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
{
- return max_longs && static_cpu_has(X86_FEATURE_RDRAND) && rdrand_long(v) ? 1 : 0;
+ return max_longs && cpu_feature_enabled(X86_FEATURE_RDRAND) && rdrand_long(v) ? 1 : 0;
}
static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
{
- return max_longs && static_cpu_has(X86_FEATURE_RDSEED) && rdseed_long(v) ? 1 : 0;
+ return max_longs && cpu_feature_enabled(X86_FEATURE_RDSEED) && rdseed_long(v) ? 1 : 0;
}
#ifndef CONFIG_UML
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 90680f978d43..b4cc5fd1ba2c 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -69,7 +69,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
* is not relevant.
*/
#define cpu_feature_enabled(bit) \
- (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit))
+ (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : _static_cpu_has(bit))
#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
@@ -96,7 +96,7 @@ void check_cpufeature_deps(struct cpuinfo_x86 *c);
* it to manifest the address of boot_cpu_data in a register, fouling
* the mainline (post-initialization) code.
*/
-static __always_inline bool _static_cpu_has(u16 bit)
+static __always_inline bool __static_cpu_has(u16 bit)
{
asm goto(ALTERNATIVE_TERNARY("jmp 6f", %c[feature], "", "jmp %l[t_no]")
".pushsection .altinstr_aux,\"ax\"\n"
@@ -116,17 +116,17 @@ static __always_inline bool _static_cpu_has(u16 bit)
return false;
}
-#define static_cpu_has(bit) \
+#define _static_cpu_has(bit) \
( \
__builtin_constant_p(boot_cpu_has(bit)) ? \
boot_cpu_has(bit) : \
- _static_cpu_has(bit) \
+ __static_cpu_has(bit) \
)
#define cpu_has_bug(c, bit) cpu_has(c, (bit))
#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit))
-#define static_cpu_has_bug(bit) static_cpu_has((bit))
+#define static_cpu_has_bug(bit) _static_cpu_has((bit))
#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit))
#define boot_cpu_set_bug(bit) set_cpu_cap(&boot_cpu_data, (bit))
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index a2c1f2d24b64..854d82b88ff4 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -129,7 +129,7 @@ static __always_inline unsigned long local_db_save(void)
{
unsigned long dr7;
- if (static_cpu_has(X86_FEATURE_HYPERVISOR) && !hw_breakpoint_active())
+ if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR) && !hw_breakpoint_active())
return 0;
get_debugreg(dr7, 7);
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index ac295ca6c92f..9368f1a33c30 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -911,7 +911,7 @@ pgd_t __pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd);
*/
static inline pgd_t pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd)
{
- if (!static_cpu_has(X86_FEATURE_PTI))
+ if (!cpu_feature_enabled(X86_FEATURE_PTI))
return pgd;
return __pti_set_user_pgtbl(pgdp, pgd);
}
@@ -1471,7 +1471,7 @@ static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
{
memcpy(dst, src, count * sizeof(pgd_t));
#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
- if (!static_cpu_has(X86_FEATURE_PTI))
+ if (!cpu_feature_enabled(X86_FEATURE_PTI))
return;
/* Clone the user space pgd as well */
memcpy(kernel_to_user_pgdp(dst), kernel_to_user_pgdp(src),
diff --git a/arch/x86/include/asm/sync_core.h b/arch/x86/include/asm/sync_core.h
index 96bda43538ee..df22113db9cd 100644
--- a/arch/x86/include/asm/sync_core.h
+++ b/arch/x86/include/asm/sync_core.h
@@ -61,7 +61,7 @@ static __always_inline void sync_core(void)
* The SERIALIZE instruction is the most straightforward way to
* do this, but it is not universally available.
*/
- if (static_cpu_has(X86_FEATURE_SERIALIZE)) {
+ if (cpu_feature_enabled(X86_FEATURE_SERIALIZE)) {
serialize();
return;
}
@@ -96,7 +96,7 @@ static __always_inline void sync_core(void)
static inline void sync_core_before_usermode(void)
{
/* With PTI, we unconditionally serialize before running user code. */
- if (static_cpu_has(X86_FEATURE_PTI))
+ if (cpu_feature_enabled(X86_FEATURE_PTI))
return;
/*
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 5c5be2d58242..a60c8960bbfd 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -31,7 +31,7 @@ static u32 numachip1_get_apic_id(u32 x)
unsigned long value;
unsigned int id = (x >> 24) & 0xff;
- if (static_cpu_has(X86_FEATURE_NODEID_MSR)) {
+ if (cpu_feature_enabled(X86_FEATURE_NODEID_MSR)) {
rdmsrq(MSR_FAM10H_NODE_ID, value);
id |= (value << 2) & 0xff00;
}
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 83f51cab0b1e..0377f58536a6 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -191,8 +191,8 @@ x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool setguest)
* If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
* MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
*/
- if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
- !static_cpu_has(X86_FEATURE_VIRT_SSBD))
+ if (!cpu_feature_enabled(X86_FEATURE_LS_CFG_SSBD) &&
+ !cpu_feature_enabled(X86_FEATURE_VIRT_SSBD))
return;
/*
@@ -200,7 +200,7 @@ x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool setguest)
* virtual MSR value. If its not permanently enabled, evaluate
* current's TIF_SSBD thread flag.
*/
- if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
+ if (cpu_feature_enabled(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
hostval = SPEC_CTRL_SSBD;
else
hostval = ssbd_tif_to_spec_ctrl(ti->flags);
@@ -2457,8 +2457,8 @@ static void __init ssb_apply_mitigation(void)
* Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
* use a completely different MSR and bit dependent on family.
*/
- if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
- !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
+ if (!cpu_feature_enabled(X86_FEATURE_SPEC_CTRL_SSBD) &&
+ !cpu_feature_enabled(X86_FEATURE_AMD_SSBD)) {
x86_amd_ssb_disable();
} else {
x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 51a95b07831f..13ed16527905 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -654,7 +654,7 @@ static DEFINE_RAW_SPINLOCK(cache_disable_lock);
*/
static void maybe_flush_caches(void)
{
- if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
+ if (!cpu_feature_enabled(X86_FEATURE_SELFSNOOP))
wbinvd();
}
diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c
index 584fb9913be4..3f31fb06c9eb 100644
--- a/arch/x86/kernel/fpu/core.c
+++ b/arch/x86/kernel/fpu/core.c
@@ -874,7 +874,7 @@ void fpu_flush_thread(void)
*/
void switch_fpu_return(void)
{
- if (!static_cpu_has(X86_FEATURE_FPU))
+ if (!cpu_feature_enabled(X86_FEATURE_FPU))
return;
fpregs_restore_userregs();
diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c
index 20b638c507ca..33e1284bf3e4 100644
--- a/arch/x86/kernel/fpu/signal.c
+++ b/arch/x86/kernel/fpu/signal.c
@@ -187,7 +187,7 @@ bool copy_fpstate_to_sigframe(void __user *buf, void __user *buf_fx, int size, u
ia32_fxstate &= (IS_ENABLED(CONFIG_X86_32) ||
IS_ENABLED(CONFIG_IA32_EMULATION));
- if (!static_cpu_has(X86_FEATURE_FPU)) {
+ if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
struct user_i387_ia32_struct fp;
fpregs_soft_get(current, NULL, (struct membuf){.p = &fp,
diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c
index 6f826a00eca2..c994b0745983 100644
--- a/arch/x86/kernel/kprobes/opt.c
+++ b/arch/x86/kernel/kprobes/opt.c
@@ -77,7 +77,7 @@ unsigned long __recover_optprobed_insn(kprobe_opcode_t *buf, unsigned long addr)
static void synthesize_clac(kprobe_opcode_t *addr)
{
/*
- * Can't be static_cpu_has() due to how objtool treats this feature bit.
+ * Can't be cpu_feature_enabled() due to how objtool treats this feature bit.
* This isn't a fast path anyway.
*/
if (!boot_cpu_has(X86_FEATURE_SMAP))
diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c
index 40c5bf97dd5c..4fa7a86adece 100644
--- a/arch/x86/kernel/ldt.c
+++ b/arch/x86/kernel/ldt.c
@@ -61,7 +61,7 @@ void load_mm_ldt(struct mm_struct *mm)
*/
if (unlikely(ldt)) {
- if (static_cpu_has(X86_FEATURE_PTI)) {
+ if (cpu_feature_enabled(X86_FEATURE_PTI)) {
if (WARN_ON_ONCE((unsigned long)ldt->slot > 1)) {
/*
* Whoops -- either the new LDT isn't mapped
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index a554f19c9973..10f057881ac4 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -578,7 +578,7 @@ static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
struct ssb_state *st = this_cpu_ptr(&ssb_state);
u64 msr = x86_amd_ls_cfg_base;
- if (!static_cpu_has(X86_FEATURE_ZEN)) {
+ if (!cpu_feature_enabled(X86_FEATURE_ZEN)) {
msr |= ssbd_tif_to_amd_ls_cfg(tifn);
wrmsrq(MSR_AMD64_LS_CFG, msr);
return;
@@ -645,14 +645,14 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp,
lockdep_assert_irqs_disabled();
/* Handle change of TIF_SSBD depending on the mitigation method. */
- if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
+ if (cpu_feature_enabled(X86_FEATURE_VIRT_SSBD)) {
if (tif_diff & _TIF_SSBD)
amd_set_ssb_virt_state(tifn);
- } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
+ } else if (cpu_feature_enabled(X86_FEATURE_LS_CFG_SSBD)) {
if (tif_diff & _TIF_SSBD)
amd_set_core_ssb_state(tifn);
- } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
- static_cpu_has(X86_FEATURE_AMD_SSBD)) {
+ } else if (cpu_feature_enabled(X86_FEATURE_SPEC_CTRL_SSBD) ||
+ cpu_feature_enabled(X86_FEATURE_AMD_SSBD)) {
updmsr |= !!(tif_diff & _TIF_SSBD);
msr |= ssbd_tif_to_spec_ctrl(tifn);
}
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index d44afbe005bb..2bce7b3f97ed 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -277,7 +277,7 @@ static __always_inline void save_fsgs(struct task_struct *task)
{
savesegment(fs, task->thread.fsindex);
savesegment(gs, task->thread.gsindex);
- if (static_cpu_has(X86_FEATURE_FSGSBASE)) {
+ if (cpu_feature_enabled(X86_FEATURE_FSGSBASE)) {
/*
* If FSGSBASE is enabled, we can't make any useful guesses
* about the base, and user code expects us to save the current
@@ -391,7 +391,7 @@ static __always_inline void x86_pkru_load(struct thread_struct *prev,
static __always_inline void x86_fsgsbase_load(struct thread_struct *prev,
struct thread_struct *next)
{
- if (static_cpu_has(X86_FEATURE_FSGSBASE)) {
+ if (cpu_feature_enabled(X86_FEATURE_FSGSBASE)) {
/* Update the FS and GS selectors if they could have changed. */
if (unlikely(prev->fsindex || next->fsindex))
loadseg(FS, next->fsindex);
@@ -533,7 +533,7 @@ start_thread_common(struct pt_regs *regs, unsigned long new_ip,
{
WARN_ON_ONCE(regs != current_pt_regs());
- if (static_cpu_has(X86_BUG_NULL_SEG)) {
+ if (cpu_feature_enabled(X86_BUG_NULL_SEG)) {
/* Loading zero below won't clear the base. */
loadsegment(fs, __USER_DS);
load_gs_index(__USER_DS);
diff --git a/arch/x86/kernel/signal_32.c b/arch/x86/kernel/signal_32.c
index e55cf19e68fe..8e87ab586437 100644
--- a/arch/x86/kernel/signal_32.c
+++ b/arch/x86/kernel/signal_32.c
@@ -357,7 +357,7 @@ int ia32_setup_rt_frame(struct ksignal *ksig, struct pt_regs *regs)
unsafe_put_user(ptr_to_compat(&frame->uc), &frame->puc, Efault);
/* Create the ucontext. */
- if (static_cpu_has(X86_FEATURE_XSAVE))
+ if (cpu_feature_enabled(X86_FEATURE_XSAVE))
unsafe_put_user(UC_FP_XSTATE, &frame->uc.uc_flags, Efault);
else
unsafe_put_user(0, &frame->uc.uc_flags, Efault);
diff --git a/arch/x86/kernel/time.c b/arch/x86/kernel/time.c
index 52e1f3f0b361..4061430ac74c 100644
--- a/arch/x86/kernel/time.c
+++ b/arch/x86/kernel/time.c
@@ -82,7 +82,7 @@ static __init void x86_late_time_init(void)
x86_init.irqs.intr_mode_init();
tsc_init();
- if (static_cpu_has(X86_FEATURE_WAITPKG))
+ if (cpu_feature_enabled(X86_FEATURE_WAITPKG))
use_tpause_delay();
}
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index 74e336d7f9dd..81e113eb7c7c 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -221,7 +221,7 @@ SECTIONS
* references to such code must be patched out by alternatives, normally
* by using X86_FEATURE_ALWAYS CPU feature bit.
*
- * See static_cpu_has() for an example.
+ * See cpu_feature_enabled() for an example.
*/
.altinstr_aux : AT(ADDR(.altinstr_aux) - LOAD_OFFSET) {
*(.altinstr_aux)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index e69156b54cff..1642417c7465 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1507,7 +1507,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
union cpuid10_eax eax = { };
union cpuid10_edx edx = { };
- if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
+ if (!enable_pmu || !cpu_feature_enabled(X86_FEATURE_ARCH_PERFMON)) {
entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
break;
}
@@ -1748,7 +1748,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
* loop if said highest leaf has no subleaves indexed by ECX.
*/
if (entry->eax >= 0x8000001d &&
- (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)
+ (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)
|| !static_cpu_has_bug(X86_BUG_NULL_SEG)))
entry->eax = max(entry->eax, 0x80000021);
break;
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index d38a21be099d..ddaf6ce73c24 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -306,7 +306,7 @@ static int __svm_skip_emulated_instruction(struct kvm_vcpu *vcpu,
goto done;
if (nrips && svm->vmcb->control.next_rip != 0) {
- WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
+ WARN_ON_ONCE(!cpu_feature_enabled(X86_FEATURE_NRIPS));
svm->next_rip = svm->vmcb->control.next_rip;
}
@@ -376,7 +376,7 @@ static int svm_update_soft_interrupt_rip(struct kvm_vcpu *vcpu, u8 vector)
if (nrips)
kvm_rip_write(vcpu, old_rip);
- if (static_cpu_has(X86_FEATURE_NRIPS))
+ if (cpu_feature_enabled(X86_FEATURE_NRIPS))
svm->vmcb->control.next_rip = rip;
return 0;
@@ -574,7 +574,7 @@ static int svm_enable_virtualization_cpu(void)
wrmsrq(MSR_VM_HSAVE_PA, sd->save_area_pa);
- if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
+ if (cpu_feature_enabled(X86_FEATURE_TSCRATEMSR)) {
/*
* Set the default value, even if we don't use TSC scaling
* to avoid having stale value in the msr
@@ -1955,7 +1955,7 @@ static int pf_interception(struct kvm_vcpu *vcpu)
u64 error_code = svm->vmcb->control.exit_info_1;
return kvm_handle_page_fault(vcpu, error_code, fault_address,
- static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
+ cpu_feature_enabled(X86_FEATURE_DECODEASSISTS) ?
svm->vmcb->control.insn_bytes : NULL,
svm->vmcb->control.insn_len);
}
@@ -2003,7 +2003,7 @@ static int npf_interception(struct kvm_vcpu *vcpu)
trace_kvm_page_fault(vcpu, gpa, error_code);
rc = kvm_mmu_page_fault(vcpu, gpa, error_code,
- static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
+ cpu_feature_enabled(X86_FEATURE_DECODEASSISTS) ?
svm->vmcb->control.insn_bytes : NULL,
svm->vmcb->control.insn_len);
@@ -2512,7 +2512,7 @@ static int iret_interception(struct kvm_vcpu *vcpu)
static int invlpg_interception(struct kvm_vcpu *vcpu)
{
- if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
+ if (!cpu_feature_enabled(X86_FEATURE_DECODEASSISTS))
return kvm_emulate_instruction(vcpu, 0);
kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
@@ -2560,7 +2560,7 @@ static int cr_interception(struct kvm_vcpu *vcpu)
unsigned long val;
int err;
- if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
+ if (!cpu_feature_enabled(X86_FEATURE_DECODEASSISTS))
return emulate_on_interception(vcpu);
if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
@@ -4145,7 +4145,7 @@ static void svm_flush_tlb_asid(struct kvm_vcpu *vcpu)
* unconditionally does a TLB flush on both nested VM-Enter and nested
* VM-Exit (via kvm_mmu_reset_context()).
*/
- if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
+ if (cpu_feature_enabled(X86_FEATURE_FLUSHBYASID))
svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
else
svm->current_vmcb->asid_generation--;
@@ -4506,12 +4506,12 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu, u64 run_flags)
* is no need to worry about the conditional branch over the wrmsr
* being speculatively taken.
*/
- if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
+ if (!cpu_feature_enabled(X86_FEATURE_V_SPEC_CTRL))
x86_spec_ctrl_set_guest(svm->virt_spec_ctrl);
svm_vcpu_enter_exit(vcpu, spec_ctrl_intercepted);
- if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
+ if (!cpu_feature_enabled(X86_FEATURE_V_SPEC_CTRL))
x86_spec_ctrl_restore_host(svm->virt_spec_ctrl);
if (!is_sev_es_guest(vcpu)) {
@@ -4877,7 +4877,7 @@ static int svm_check_intercept(struct kvm_vcpu *vcpu,
}
/* TODO: Advertise NRIPS to guest hypervisor unconditionally */
- if (static_cpu_has(X86_FEATURE_NRIPS))
+ if (cpu_feature_enabled(X86_FEATURE_NRIPS))
vmcb->control.next_rip = info->next_rip;
vmcb->control.exit_code = icpt_info.exit_code;
vmexit = nested_svm_exit_handled(svm);
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index ede773ce065a..fa7ddeb60434 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -416,7 +416,7 @@ static noinstr void vmx_l1d_flush(struct kvm_vcpu *vcpu)
vcpu->stat.l1d_flush++;
- if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
+ if (cpu_feature_enabled(X86_FEATURE_FLUSH_L1D)) {
native_wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
return;
}
@@ -1799,7 +1799,7 @@ static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
* (namely Hyper-V) don't set it due to it being undefined behavior,
* i.e. we end up advancing IP with some random value.
*/
- if (!static_cpu_has(X86_FEATURE_HYPERVISOR) ||
+ if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR) ||
exit_reason.basic != EXIT_REASON_EPT_MISCONFIG) {
instr_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
@@ -8801,7 +8801,7 @@ __init int vmx_hardware_setup(void)
* caches properly. This also requires honoring guest PAT, and is forced
* independent of the quirk in vmx_ignore_guest_pat().
*/
- if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
+ if (!cpu_feature_enabled(X86_FEATURE_SELFSNOOP))
kvm_caps.supported_quirks &= ~KVM_X86_QUIRK_IGNORE_GUEST_PAT;
kvm_caps.inapplicable_quirks &= ~KVM_X86_QUIRK_IGNORE_GUEST_PAT;
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 0550359ed798..562ea5ce8fc3 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1785,7 +1785,7 @@ static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
kvm_mmu_reset_context(vcpu);
- if (!static_cpu_has(X86_FEATURE_XSAVES) &&
+ if (!cpu_feature_enabled(X86_FEATURE_XSAVES) &&
(efer & EFER_SVME))
kvm_hv_xsaves_xsavec_maybe_warn(vcpu);
@@ -3202,7 +3202,7 @@ static void kvm_update_masterclock(struct kvm *kvm)
*/
static unsigned long get_cpu_tsc_khz(void)
{
- if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
+ if (cpu_feature_enabled(X86_FEATURE_CONSTANT_TSC))
return tsc_khz;
else
return __this_cpu_read(cpu_tsc_khz);
@@ -3219,7 +3219,7 @@ static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
data->flags = 0;
if (ka->use_master_clock &&
- (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
+ (cpu_feature_enabled(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
#ifdef CONFIG_X86_64
struct timespec64 ts;
diff --git a/arch/x86/kvm/xen.c b/arch/x86/kvm/xen.c
index 91fd3673c09a..06eb70493405 100644
--- a/arch/x86/kvm/xen.c
+++ b/arch/x86/kvm/xen.c
@@ -212,7 +212,7 @@ static void kvm_xen_start_timer(struct kvm_vcpu *vcpu, u64 guest_abs,
struct pvclock_vcpu_time_info hv_clock;
uint64_t host_tsc, guest_tsc;
- if (!static_cpu_has(X86_FEATURE_CONSTANT_TSC) ||
+ if (!cpu_feature_enabled(X86_FEATURE_CONSTANT_TSC) ||
!vcpu->kvm->arch.use_master_clock)
break;
diff --git a/arch/x86/lib/copy_mc.c b/arch/x86/lib/copy_mc.c
index 97e88e58567b..d509256a228e 100644
--- a/arch/x86/lib/copy_mc.c
+++ b/arch/x86/lib/copy_mc.c
@@ -70,7 +70,7 @@ unsigned long __must_check copy_mc_to_kernel(void *dst, const void *src, unsigne
instrument_memcpy_after(dst, src, len, ret);
return ret;
}
- if (static_cpu_has(X86_FEATURE_ERMS)) {
+ if (cpu_feature_enabled(X86_FEATURE_ERMS)) {
instrument_memcpy_before(dst, src, len);
ret = copy_mc_enhanced_fast_string(dst, src, len);
instrument_memcpy_after(dst, src, len, ret);
@@ -93,7 +93,7 @@ unsigned long __must_check copy_mc_to_user(void __user *dst, const void *src, un
return ret;
}
- if (static_cpu_has(X86_FEATURE_ERMS)) {
+ if (cpu_feature_enabled(X86_FEATURE_ERMS)) {
instrument_copy_to_user(dst, src, len);
__uaccess_begin();
ret = copy_mc_enhanced_fast_string((__force void *)dst, src, len);
diff --git a/arch/x86/lib/usercopy_32.c b/arch/x86/lib/usercopy_32.c
index ac27e39fc993..b4c13493c645 100644
--- a/arch/x86/lib/usercopy_32.c
+++ b/arch/x86/lib/usercopy_32.c
@@ -328,7 +328,7 @@ unsigned long copy_from_user_inatomic_nontemporal(void *to, const void __user *f
if (!user_access_begin(from, n))
return n;
#ifdef CONFIG_X86_INTEL_USERCOPY
- if (n > 64 && static_cpu_has(X86_FEATURE_XMM2))
+ if (n > 64 && cpu_feature_enabled(X86_FEATURE_XMM2))
n = __copy_user_intel_nocache(to, from, n);
else
__copy_user(to, from, n);
diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c
index ceb8d03191ab..fa6eebe6a69e 100644
--- a/arch/x86/mm/extable.c
+++ b/arch/x86/mm/extable.c
@@ -194,7 +194,7 @@ static bool ex_handler_msr(const struct exception_table_entry *fixup,
static bool ex_handler_clear_fs(const struct exception_table_entry *fixup,
struct pt_regs *regs)
{
- if (static_cpu_has(X86_BUG_NULL_SEG))
+ if (cpu_feature_enabled(X86_BUG_NULL_SEG))
asm volatile ("mov %0, %%fs" : : "rm" (__USER_DS));
asm volatile ("mov %0, %%fs" : : "rm" (0));
return ex_handler_default(fixup, regs);
diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
index d023a40a1e03..dc7c904b032e 100644
--- a/arch/x86/mm/pat/set_memory.c
+++ b/arch/x86/mm/pat/set_memory.c
@@ -448,7 +448,7 @@ static void cpa_flush(struct cpa_data *cpa, int cache)
BUG_ON(irqs_disabled() && !early_boot_irqs_disabled);
- if (cache && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
+ if (cache && !cpu_feature_enabled(X86_FEATURE_CLFLUSH)) {
cpa_flush_all(cache);
goto collapse_large_pages;
}
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 1023acadd8f8..cacd2c3f78eb 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -162,7 +162,7 @@ static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam)
{
unsigned long cr3 = __sme_pa(pgd) | lam;
- if (static_cpu_has(X86_FEATURE_PCID)) {
+ if (cpu_feature_enabled(X86_FEATURE_PCID)) {
cr3 |= kern_pcid(asid);
} else {
VM_WARN_ON_ONCE(asid != 0);
@@ -197,7 +197,7 @@ static void clear_asid_other(void)
* This is only expected to be set if we have disabled
* kernel _PAGE_GLOBAL pages.
*/
- if (!static_cpu_has(X86_FEATURE_PTI)) {
+ if (!cpu_feature_enabled(X86_FEATURE_PTI)) {
WARN_ON_ONCE(1);
return;
}
@@ -227,7 +227,7 @@ static struct new_asid choose_new_asid(struct mm_struct *next, u64 next_tlb_gen)
struct new_asid ns;
u16 asid;
- if (!static_cpu_has(X86_FEATURE_PCID)) {
+ if (!cpu_feature_enabled(X86_FEATURE_PCID)) {
ns.asid = 0;
ns.need_flush = 1;
return ns;
@@ -555,7 +555,7 @@ static inline void invalidate_user_asid(u16 asid)
if (!cpu_feature_enabled(X86_FEATURE_PCID))
return;
- if (!static_cpu_has(X86_FEATURE_PTI))
+ if (!cpu_feature_enabled(X86_FEATURE_PTI))
return;
__set_bit(kern_pcid(asid),
@@ -1584,7 +1584,7 @@ void flush_tlb_one_kernel(unsigned long addr)
*/
flush_tlb_one_user(addr);
- if (!static_cpu_has(X86_FEATURE_PTI))
+ if (!cpu_feature_enabled(X86_FEATURE_PTI))
return;
/*
@@ -1608,7 +1608,7 @@ STATIC_NOPV void native_flush_tlb_one_user(unsigned long addr)
invlpg(addr);
/* If PTI is off there is no user PCID and nothing to flush. */
- if (!static_cpu_has(X86_FEATURE_PTI))
+ if (!cpu_feature_enabled(X86_FEATURE_PTI))
return;
loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
@@ -1637,7 +1637,7 @@ STATIC_NOPV void native_flush_tlb_global(void)
{
unsigned long flags;
- if (static_cpu_has(X86_FEATURE_INVPCID)) {
+ if (cpu_feature_enabled(X86_FEATURE_INVPCID)) {
/*
* Using INVPCID is considerably faster than a pair of writes
* to CR4 sandwiched inside an IRQ flag save/restore.
diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c
index 8153d62c58f0..4ab697014bf4 100644
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
@@ -307,7 +307,7 @@ static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev
const struct pci_dev *pcie_to_pci_bridge;
// Detect any type of AMD Ryzen machine.
- if (!static_cpu_has(X86_FEATURE_ZEN))
+ if (!cpu_feature_enabled(X86_FEATURE_ZEN))
return false;
// Detect VIA VT6306/6307/6308.
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index ea1d2d5d2c66..2eed55b46e29 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -88,7 +88,7 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages)
{
#if defined(CONFIG_X86)
- if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
+ if (cpu_feature_enabled(X86_FEATURE_CLFLUSH)) {
drm_cache_flush_clflush(pages, num_pages);
return;
}
@@ -127,7 +127,7 @@ void
drm_clflush_sg(struct sg_table *st)
{
#if defined(CONFIG_X86)
- if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
+ if (cpu_feature_enabled(X86_FEATURE_CLFLUSH)) {
struct sg_page_iter sg_iter;
mb(); /*CLFLUSH is ordered only by using memory barriers*/
@@ -157,7 +157,7 @@ void
drm_clflush_virt_range(void *addr, unsigned long length)
{
#if defined(CONFIG_X86)
- if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
+ if (cpu_feature_enabled(X86_FEATURE_CLFLUSH)) {
const int size = boot_cpu_data.x86_clflush_size;
void *end = addr + length;
@@ -332,7 +332,7 @@ void drm_memcpy_init_early(void)
* Some hypervisors (e.g. KVM) don't support VEX-prefix instructions
* emulation. So don't enable movntdqa in hypervisor guest.
*/
- if (static_cpu_has(X86_FEATURE_XMM4_1) &&
+ if (cpu_feature_enabled(X86_FEATURE_XMM4_1) &&
!boot_cpu_has(X86_FEATURE_HYPERVISOR))
static_branch_enable(&has_movntdqa);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index df7502391b50..b7297c0a3a48 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -681,7 +681,7 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj,
return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ ||
- !static_cpu_has(X86_FEATURE_CLFLUSH)) {
+ !cpu_feature_enabled(X86_FEATURE_CLFLUSH)) {
ret = i915_gem_object_set_to_cpu_domain(obj, false);
if (ret)
goto err_unpin;
@@ -732,7 +732,7 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj,
return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE ||
- !static_cpu_has(X86_FEATURE_CLFLUSH)) {
+ !cpu_feature_enabled(X86_FEATURE_CLFLUSH)) {
ret = i915_gem_object_set_to_cpu_domain(obj, true);
if (ret)
goto err_unpin;
diff --git a/drivers/gpu/drm/i915/i915_memcpy.c b/drivers/gpu/drm/i915/i915_memcpy.c
index cc41974cee74..20433621e09a 100644
--- a/drivers/gpu/drm/i915/i915_memcpy.c
+++ b/drivers/gpu/drm/i915/i915_memcpy.c
@@ -166,7 +166,7 @@ void i915_memcpy_init_early(struct drm_i915_private *dev_priv)
* Some hypervisors (e.g. KVM) don't support VEX-prefix instructions
* emulation. So don't enable movntdqa in hypervisor guest.
*/
- if (static_cpu_has(X86_FEATURE_XMM4_1) &&
+ if (cpu_feature_enabled(X86_FEATURE_XMM4_1) &&
!boot_cpu_has(X86_FEATURE_HYPERVISOR))
static_branch_enable(&has_movntdqa);
}
diff --git a/drivers/md/dm-writecache.c b/drivers/md/dm-writecache.c
index 493f5202ad04..302b60793da2 100644
--- a/drivers/md/dm-writecache.c
+++ b/drivers/md/dm-writecache.c
@@ -1227,7 +1227,7 @@ static void memcpy_flushcache_optimized(void *dest, void *source, size_t size)
* advantage seen with cache-allocating-writes plus flushing.
*/
#ifdef CONFIG_X86
- if (static_cpu_has(X86_FEATURE_CLFLUSHOPT) &&
+ if (cpu_feature_enabled(X86_FEATURE_CLFLUSHOPT) &&
likely(boot_cpu_data.x86_clflush_size == 64) &&
likely(size >= 768)) {
do {
diff --git a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
index b804cb753f94..3bd16ea07461 100644
--- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
+++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
@@ -558,7 +558,7 @@ static bool disable_dynamic_sst_features(void)
{
u64 value;
- if (!static_cpu_has(X86_FEATURE_HWP))
+ if (!cpu_feature_enabled(X86_FEATURE_HWP))
return true;
rdmsrq(MSR_PM_ENABLE, value);
diff --git a/drivers/thermal/intel/therm_throt.c b/drivers/thermal/intel/therm_throt.c
index 44fa4dd15dd1..bd09d9462c72 100644
--- a/drivers/thermal/intel/therm_throt.c
+++ b/drivers/thermal/intel/therm_throt.c
@@ -652,7 +652,7 @@ void intel_thermal_interrupt(void)
{
__u64 msr_val;
- if (static_cpu_has(X86_FEATURE_HWP))
+ if (cpu_feature_enabled(X86_FEATURE_HWP))
notify_hwp_interrupt();
rdmsrq(MSR_IA32_THERM_STATUS, msr_val);
--
2.53.0
reply other threads:[~2026-06-20 1:50 UTC|newest]
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