From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41E9218A92F for ; Sat, 20 Jun 2026 20:46:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781988388; cv=none; b=I6CkGdlVgmM+XkslmocuCr/jHWsDmHY9pUsGjSaudHa4RZldMOJVlokf+q9xfbTnzLJMpltEE2uu2e14t7NHuaWJAbW2CqVRWQ8pZrjLc+G15LhaUnu+rk2nihzHA0SVJYHhJ6OKC9RXo2Orhci/TCstchQpbkChqMJF/uMGV/4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781988388; c=relaxed/simple; bh=9OMddAER8ysz3qOphHy6Ge8vDf6Hkw0cENlUlI5UDd0=; h=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date: Message-Id; b=s/Obp/Gu/shuqH13xlPEsqgQdfYEJr2JFri0bRbBDaiMH9ueeUcg2rkBdX0OxwHJFrJiZl9s6kSvK1Jp0XPfFJgx/EfRU/kydtXbqkIHh8XMiU+JMvkA+KPrTB+HyEbH+xA9bOtuv0g/luhgVEiuhZQPGhvVgX3Gj8shBDs9vVo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Mk2kZQXc; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Mk2kZQXc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7DE9A1F000E9; Sat, 20 Jun 2026 20:46:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781988386; bh=vPICMI/UV/75uJe7FMSSCUWpFqObmysiYXdJkO2Co5o=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=Mk2kZQXcQiI16Xe1AARCpVc9cuGlpK5PZ0WyQDULU5v7ll8GNAtgWSfFvlSBI6rdL MU4dWckv9tGWDJGJ6DxAnArwFzAINHVql72w2ZubtnWNrD70A7llzxSx0jChSDQDNa sr0JOxP0JpTurFGkJ1AKI/AC8RHCkNHL+GMW2bS5zi82QUo5EP9WcR34HoJCPLVIq/ asu/qk7vv0UgyjknhFc7ZecWu+1Fh7SSxPZ9AJ/X0kZc8xTm3jWrxbiQfUKZOVQ7Kk rdD4WLJOnWqbHxDevTFl+ZgJdr2Ggzi83J10nul7tP+a5/lbN1Ticf9GEMoPOOTX2d AgO+GGtHQDMLA== From: sashiko-bot@kernel.org Subject: Re: [PATCH RESEND 3/3] dmaengine: xilinx_dma: Optimize control register write and channel start logic for AXIDMA and MCDMA in corresponding start_transfer() Reply-To: sashiko-reviews@lists.linux.dev To: "Suraj Gupta" Cc: vkoul@kernel.org, dmaengine@vger.kernel.org, Frank.Li@kernel.org In-Reply-To: <20260620203417.4000360-4-suraj.gupta2@amd.com> References: <20260620203417.4000360-1-suraj.gupta2@amd.com> <20260620203417.4000360-4-suraj.gupta2@amd.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Sat, 20 Jun 2026 20:46:25 +0000 Message-Id: <20260620204626.7DE9A1F000E9@smtp.kernel.org> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 1 potential issue(= s) to consider: Pre-existing issues: - [High] Concurrent read-modify-write on shared global MCDMA registers due = to lack of a controller-level lock. -- commit ecde894a65e016199009c2bd5c7fcf89cdab08cf Author: Suraj Gupta dmaengine: xilinx_dma: Optimize control register write and channel start lo= gic for AXIDMA and MCDMA in corresponding start_transfer() This commit optimizes AXI DMA control register programming by combining coalesce count and delay configuration into a single register write to reduce bus overhead. It also avoids redundant channel starts by only calling xilinx_dma_start() when the channel is actually idle. > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_= dma.c > index 35b553ee3205c..aa3dee0dc2fcb 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c [ ... ] > @@ -1693,7 +1693,8 @@ static void xilinx_mcdma_start_transfer(struct xili= nx_dma_chan *chan) > reg |=3D XILINX_MCDMA_CR_RUNSTOP_MASK; > dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); > =20 > - xilinx_dma_start(chan); > + if (chan->idle) > + xilinx_dma_start(chan); [Severity: High] This is a pre-existing issue, but does the lack of a controller-level lock cause concurrent read-modify-write operations on shared global MCDMA registers to race? In xilinx_mcdma_start_transfer(), just before this diff context, there is an unprotected read-modify-write on the shared XILINX_MCDMA_CHEN_OFFSET register: reg =3D dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); reg |=3D BIT(chan->tdest); dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg); Similarly, when xilinx_dma_start() is called here, it performs an unprotected read-modify-write on the shared XILINX_DMA_REG_DMACR register: dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); These operations appear to be protected only by the per-channel spinlock (chan->lock). If two channels on the same controller execute their start transfer logic concurrently on different CPUs, can the read-modify-write operations race and lead to a channel's enable bit being silently overwritten and lost? --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260620203417.4000= 360-1-suraj.gupta2@amd.com?part=3D3