Re: [PATCH v6 5/8] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing regulator specifications for non-PCIe clocks (EDP, USB) in Mahua TCSR descriptors
--

commit 6c7380c66661cd5b69976b7e56fdb61f281c6291
Author: Qiang Yu <qiang.yu@oss.qualcomm.com>

clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support

This commit adds Mahua-specific regulator arrays and clock descriptor tables
for PCIe clock references. It uses match_data to select the correct descriptor
table based on the compatible string during probe.

> diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c
> index 2db039342f300..9af520b71f315 100644
> --- a/drivers/clk/qcom/tcsrcc-glymur.c
> +++ b/drivers/clk/qcom/tcsrcc-glymur.c
[ ... ]
> +static const struct qcom_clk_ref_desc tcsr_cc_mahua_clk_descs[] = {
> +	[TCSR_EDP_CLKREF_EN] = {
> +		.name = "tcsr_edp_clkref_en",
> +		.offset = 0x60,
> +	},
> +	[TCSR_PCIE_2_CLKREF_EN] = {
> +		.name = "tcsr_pcie_2_clkref_en",
> +		.offset = 0x4c,
> +		.regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators,
> +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators),
> +	},
[ ... ]
> +	[TCSR_USB4_1_CLKREF_EN] = {
> +		.name = "tcsr_usb4_1_clkref_en",
> +		.offset = 0x44,
> +	},
> +	[TCSR_USB4_2_CLKREF_EN] = {
> +		.name = "tcsr_usb4_2_clkref_en",
> +		.offset = 0x5c,
> +	},
> +};

[Severity: High]
Do we need regulator specifications for the non-PCIe clocks (EDP, USB2, USB3,
USB4) in this descriptor table?

Since this array only populates regulator_names for the PCIe clocks, the
non-PCIe entries are left with 0 regulators.

When the USB or eDP PHY drivers call clk_prepare_enable() on their clkrefs,
will qcom_clk_ref_prepare() just set the hardware register bit and silently
skip voting for the required LDOs?

If so, does this leave the QREF block unpowered for these peripherals and
prevent the PHYs from initializing?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260621-tcsr_qref_0622-v6-0-c939c22ded0c@oss.qualcomm.com?part=5