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From: sashiko-bot@kernel.org
To: "Atish Patra" <atish.patra@linux.dev>
Cc: robh@kernel.org, devicetree@vger.kernel.org,
	linux-perf-users@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v7 05/22] RISC-V: Define indirect CSR access helpers
Date: Mon, 22 Jun 2026 08:17:39 +0000	[thread overview]
Message-ID: <20260622081739.D18951F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260622-counter_delegation-v7-5-0ba2fd34614e@meta.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Macro Variable Shadowing / Hygiene vulnerability in statement expressions
- [Medium] API Asymmetry / Hardcoded Selector in Indirect CSR Access Helpers
--

commit aa0528a3e619974b7113157843897b147ef398e9
Author: Atish Patra <atishp@rivosinc.com>

RISC-V: Define indirect CSR access helpers

The indirect CSR requires multiple instructions to read/write CSR. Add a few
helper functions for ease of usage.

> diff --git a/arch/riscv/include/asm/csr_ind.h b/arch/riscv/include/asm/csr_ind.h
> new file mode 100644
> index 0000000000000..6fd7d44dc640a
> --- /dev/null
> +++ b/arch/riscv/include/asm/csr_ind.h
> @@ -0,0 +1,44 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2024 Rivos Inc.
> + */
> +
> +#ifndef _ASM_RISCV_CSR_IND_H
> +#define _ASM_RISCV_CSR_IND_H
> +
> +#include <linux/irqflags.h>
> +
> +#include <asm/csr.h>
> +
> +#define csr_ind_read(iregcsr, iselbase, iseloff) ({		\
> +	unsigned long __value = 0;				\
> +	unsigned long __flags;					\
> +	local_irq_save(__flags);				\

[Severity: Medium]
Is there a risk of variable shadowing here? Since this macro evaluates caller
arguments inside the statement expression, passing an argument named __flags
or __value could silently shadow these local variables. 

For example, if a caller passes a variable named __flags as the iselbase
argument, local_irq_save() would save the IRQ state into the inner shadowed
__flags variable before iselbase is evaluated. 

Could these internal variables use more unique namespace prefixes to avoid
collisions?

> +	csr_write(CSR_ISELECT, (iselbase) + (iseloff));		\
> +	__value = csr_read(iregcsr);				\

[Severity: Medium]
Does this hardcoded use of CSR_ISELECT create an issue if callers use other
data registers? 

The macro allows specifying the data register via iregcsr, but hardcodes the
selector. If these macros are used with virtualized state registers like
CSR_VSIREG, the macro would write to the host's CSR_ISELECT but then read from
the guest's CSR_VSIREG using an unmodified CSR_VSISELECT.

Would it be safer to either accept the selector register as an explicit
parameter or enforce that iregcsr must be the corresponding data register?

> +	local_irq_restore(__flags);				\
> +	__value;						\
> +})
> +
> +#define csr_ind_write(iregcsr, iselbase, iseloff, value) ({	\
> +	unsigned long __flags;					\
> +	local_irq_save(__flags);				\

[Severity: Medium]
Similarly, does the local __flags variable here risk shadowing arguments
passed as iselbase, iseloff, or value?

> +	csr_write(CSR_ISELECT, (iselbase) + (iseloff));		\
> +	csr_write(iregcsr, (value));				\
> +	local_irq_restore(__flags);				\
> +})
> +
> +#define csr_ind_warl(iregcsr, iselbase, iseloff, warl_val) ({	\
> +	unsigned long __old_val = 0, __value = 0;		\
> +	unsigned long __flags;					\
> +	local_irq_save(__flags);				\

[Severity: Medium]
Does this macro have the same shadowing concerns with __old_val, __value, and
__flags colliding with the evaluated macro arguments?

> +	csr_write(CSR_ISELECT, (iselbase) + (iseloff));		\
> +	__old_val = csr_read(iregcsr);				\
> +	csr_write(iregcsr, (warl_val));				\
> +	__value = csr_read(iregcsr);				\
> +	csr_write(iregcsr, __old_val);				\
> +	local_irq_restore(__flags);				\
> +	__value;						\
> +})
> +
> +#endif

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260622-counter_delegation-v7-0-0ba2fd34614e@meta.com?part=5

  reply	other threads:[~2026-06-22  8:17 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-22  8:04 [PATCH v7 00/22] Add Counter delegation ISA extension support Atish Patra
2026-06-22  8:04 ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 01/22] RISC-V: perf: fix resource cleanup on driver probe failure Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:24   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 02/22] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 03/22] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 04/22] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 05/22] RISC-V: Define indirect CSR access helpers Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:17   ` sashiko-bot [this message]
2026-06-22  8:04 ` [PATCH v7 06/22] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:17   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 07/22] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 08/22] RISC-V: Add Sscfg extension CSR definition Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 09/22] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:18   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 10/22] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:20   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 11/22] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 12/22] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:24   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 13/22] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 14/22] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:33   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 15/22] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 16/22] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:30   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 17/22] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 18/22] RISC-V: perf: Add Qemu virt machine events Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:39   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 19/22] tools/perf: Support event code for arch standard events Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:34   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 20/22] tools/perf: Add RISC-V CounterIDMask event field Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:04 ` [PATCH v7 21/22] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:32   ` sashiko-bot
2026-06-22  8:04 ` [PATCH v7 22/22] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path Atish Patra
2026-06-22  8:04   ` Atish Patra
2026-06-22  8:35   ` sashiko-bot

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