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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4923fc47720sm497063795e9.0.2026.06.22.06.02.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2026 06:02:58 -0700 (PDT) Date: Mon, 22 Jun 2026 14:02:57 +0100 From: David Laight To: Damien Le Moal Cc: Alvin Lim , linux-ide@vger.kernel.org, Niklas Cassel , linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] ata: ahci: force 32-bit DMA for ASMedia ASM1166 Message-ID: <20260622140257.113f2275@pumpkin> In-Reply-To: <8c681e59-30aa-4a66-a5cd-9cccf8e338ff@kernel.org> References: <20260621100844.1224301-1-alvinwylim@gmail.com> <8c681e59-30aa-4a66-a5cd-9cccf8e338ff@kernel.org> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-ide@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 22 Jun 2026 20:31:54 +0900 Damien Le Moal wrote: > On 6/21/26 19:08, Alvin Lim wrote: > > The ASMedia ASM1166 SATA controller (1b21:1166) advertises 64-bit DMA > > support (AHCI CAP.S64A), but on systems with the IOMMU enabled - where it > > can be handed DMA addresses above 4 GB - it silently corrupts data in > > transit. Reads return different, wrong data on each access. SMART is clean, > > there are no SATA link resets and no MCE is raised, so the corruption is > > invisible until it surfaces as filesystem metadata errors (XFS EUCLEAN) > > or, on Ceph, mass scrub errors across multiple independent filesystems at > > once - i.e. host-level, not filesystem-level. > > > > This is the same failure mode already quirked for other controllers that > > falsely claim working 64-bit DMA. See commit 105c42566a55 ("ata: ahci: > > force 32-bit DMA for JMicron JMB582/JMB585") and commit 20730e9b2778 > > ("ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers"). > > The ASM1166 currently maps to plain board_ahci with no DMA limit. > > Have you tried the same quirk, limiting DMA to 43-bits ? It is very likely that > this adapter bug is the same as the 1061. > It would also be worth checking that you get the read fails with a 44-bit mask. I'd guess it also requires that you keep the controller busy for (about) 8TB of reads - which is where sequential address allocation would exceed 43-bits. But that is just conjecture since I've not looked at the iommu code. David