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[80.230.85.71]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-466667881bfsm30516259f8f.22.2026.06.22.13.00.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2026 13:00:20 -0700 (PDT) Date: Mon, 22 Jun 2026 16:00:17 -0400 From: "Michael S. Tsirkin" To: Peter Maydell Cc: qemu-devel@nongnu.org, Sairaj Kodilkar , Vasant Hegde , Alejandro Jimenez , Paolo Bonzini , Richard Henderson Subject: Re: [PULL 081/106] amd_iommu: Generate XT interrupts when xt support is enabled Message-ID: <20260622155957-mutt-send-email-mst@kernel.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Jun 22, 2026 at 04:19:50PM +0100, Peter Maydell wrote: > On Sun, 14 Jun 2026 at 20:09, Michael S. Tsirkin wrote: > > > > From: Sairaj Kodilkar > > > > When MMIO 0x18[IntCapXTEn]=1, interrupts originating from the IOMMU itself are > > sent based on the programming in XT IOMMU Interrupt Control Registers in MMIO > > 0x170-0x180 instead of the programming in the IOMMU's MSI capability registers. > > The guest programs these registers with appropriate vector and destination > > ID instead of writing to PCI MSI capability. > > > > Current AMD vIOMMU is capable of generating interrupts only through PCI > > MSI capability and does not care about xt mode. Because of this AMD > > vIOMMU cannot generate event log interrupts when the guest has enabled > > xt mode. > > > > Introduce a new flag "intcapxten" which is set when guest writes control > > register [IntCapXTEn] (bit 51) and use vector and destination field in > > the XT MMIO register (0x170) to support XT mode. > > Hi; Coverity points out a use of an uninitialized struct field here > (CID 1660056): > > > +static void amdvi_build_xt_msi_msg(AMDVIState *s, MSIMessage *msg) > > +{ > > + union mmio_xt_intr xt_reg; > > + struct X86IOMMUIrq irq; > > Here we declare irq, without a struct initializer... > > > + > > + xt_reg.val = amdvi_readq(s, AMDVI_MMIO_XT_GEN_INTR); > > + > > + irq.vector = xt_reg.vector; > > + irq.delivery_mode = xt_reg.delivery_mode; > > + irq.dest_mode = xt_reg.destination_mode; > > + irq.dest = (xt_reg.destination_hi << 24) | xt_reg.destination_lo; > > + irq.trigger_mode = 0; > > + irq.redir_hint = 0; > > ...and here we fill in some but not all of its fields... > > > + > > + x86_iommu_irq_to_msi_message(&irq, msg); > > ...and here we call a function which (among other things) does this: > msg.__not_used = irq->msi_addr_last_bits; > > which will read the uninitialized msi_addr_last_bits field. > > Bonus extra bug report: > > +union mmio_xt_intr { > + uint64_t val; > + struct { > + uint64_t rsvd_1:2, > + destination_mode:1, > + rsvd_2:5, > + destination_lo:24, > + vector:8, > + delivery_mode:1, > + rsvd_3:15, > + destination_hi:8; > + }; > +}; > > Please don't use bitfields like this -- this is not portable to big > endian hosts. Use the extract64() function instead, or the FIELD macros. > > I suggest something like (untested): > > (at top level in a source file or header; the numbers are > start-bit and length, check these as I may have made typos) > > FIELD(XT_GEN_INTR, DEST_MODE, 2, 1) > FIELD(XT_GEN_INTR, DEST_LO, 24, 8) > FIELD(XT_GEN_INTR, VECTOR, 32, 8) > FIELD(XT_GEN_INTR, DELIVERY_MODE, 33, 1) > FIELD(XT_GEN_INTR, DEST_HI, 49, 8) > > and then in the function you can do: > > uint64_t xtreg = amdvi_readq(s, AMDVI_MMIO_XT_GEN_INTR); > X86IOMMUIrq irq = { > .vector = FIELD_EX64(xtreg, XT_GEN_INTR, VECTOR), > .delivery_mode = FIELD_EX64(xtreg, XT_GEN_INTR, DELIVERY_MODE), > .dest_mode = FIELD_EX64(xtreg, XT_GEN_INTR, DEST_MODE), > .dest = (FIELD_X64(xtreg, XT_GEN_INTR, DEST_HI) << 24) | > FIELD_EX64(xtreg, XT_GEN_INTR, DEST_LO), > }; > > which gives you a struct initializer and you can rely on the > whole struct being initialized. > > > +} > > thanks > -- PMM Indeed. Alejandro should we revert or fix up? -- MST