From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.andi.de1.cc (mail.andi.de1.cc [178.238.236.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCA94238D52 for ; Mon, 22 Jun 2026 16:36:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.238.236.174 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782146179; cv=none; b=LxSisahnJnZpCAtG97YUW4mVvXW5fA2I4aznHBuPXFBptYIjwI1RPu9T7NuL/dsYToi1NU904Uh7vXWkjb+qwxWZRGYMGmZaUixJooasLTL+yM1oxHpB002VWqWCoisOiS/W6M+blKcRdRZuj19O80amDlzELrD721xngh1PMGY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782146179; c=relaxed/simple; bh=Trn9USfXGSWvczMyxsVFyjrNpBnNGj5YoyKyZvhn0WU=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DtuEpTxANle3dpFDLE6QGui8yl1nUQxYDe6If+WtoqQ1ReQLxlPz6PO/JIfBm0SgxdVLKfXaCojDKIuW+pNp9I9jBKdtddx5YKBCsjre5zdt43rsVfYYxzpstG6wlSCFh/kMfnGfItK9L85JVisc1Y+EV1DdY6l5x9FjfFgRK5U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kemnade.info; spf=pass smtp.mailfrom=kemnade.info; dkim=pass (2048-bit key) header.d=kemnade.info header.i=@kemnade.info header.b=9jXI7paA; arc=none smtp.client-ip=178.238.236.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kemnade.info Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kemnade.info Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kemnade.info header.i=@kemnade.info header.b="9jXI7paA" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kemnade.info; s=20220719; h=References:In-Reply-To:Subject:Cc:To:From: Reply-To:Content-ID:Content-Description; bh=wKnWeeOCic1ziv0Y+FlLgy2VKu/O8y1iY0IZvQmpxU4=; t=1782146177; x=1783355777; b=9jXI7paAEkF4FmNiZWt3/9UVSi8yZQJ9ayAHSJ2VZgy31+mGvVNHKjfCQSzFeS9fQxT2kHQuNJZ zoAxTeXgh4rXKhSOgo5j4oKiopPMQRhl5KK9/tjMokWMpUUfKB6nv3e2tPovmeg8i4Jp6k52O5GCj yulsQwwjVolWmyPQ/25VhPuTllOeBQKx8ZF+mT99kActgiAgk0oGSNn1BgArcn8+XnQ6n4OpfKwCb 3uBsZ6RWICB+DsVyEWFRtqXKtAVsufc5dFwIU+NZsaxOkP16ny7wnYHRP9m0f/Et9/h/eVO/+Dtwv Dgk/kRgD2KPQlriVUQuj1WDrxGwshOWy9nYw==; Date: Mon, 22 Jun 2026 18:35:49 +0200 From: Andreas Kemnade To: Tomi Valkeinen Cc: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson Subject: Re: [PATCH v3 05/13] drm/bridge: tc358762: Drop SPICMR write Message-ID: <20260622183549.30e17a12@kemnade.info> In-Reply-To: <25115d05-5868-45d5-9110-695347948a1f@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> <20260513-tc358762-fixes-v3-5-6698b55008b9@ideasonboard.com> <20260619082350.2ebc0cf7@kemnade.info> <20260621084150.6ea494ff@kemnade.info> <25115d05-5868-45d5-9110-695347948a1f@ideasonboard.com> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.49; aarch64-unknown-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 22 Jun 2026 10:45:17 +0300 Tomi Valkeinen wrote: > Hi, > > On 21/06/2026 09:41, Andreas Kemnade wrote: > > On Fri, 19 Jun 2026 08:23:50 +0200 > > Andreas Kemnade wrote: > > > >> On Wed, 13 May 2026 16:10:14 +0300 > >> Tomi Valkeinen wrote: > >> > >>> Drop write to SPICMR. It's unclear why the write is there, as SPI is not > >>> supported in the driver, and it's mostly just writing zeroes to already > >>> zero fields (reset defaults). None of the zero bits written disable > >>> anything wrt. SPI. > >>> > >>> Signed-off-by: Tomi Valkeinen > >> > >> Comparing it with something out of tree where SPI is apparently working. > >> It does not touch SPIMR, > >> > > ok, looking what that code really does, it sets bit 1 called SPI_SEL_CS0, > > apparently in that register. But that belongs into an spi_init function. > > Sorry, what sets bit 1? The write removed here just writes zeroes to a "Comparing it with something out of tree where SPI is apperntly working. I just wanted to correct my claim about SPIMR not being used there. That was not meant as an objection to this patch. Regards, Andreas