Re: [PATCH v3 07/13] drm/bridge: tc358762: Update comment about the number of lanes

[Andreas Kemnade <andreas@kemnade.info>]

On Mon, 22 Jun 2026 10:31:35 +0300
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> wrote:

> Hi,
> 
> On 29/05/2026 21:34, Andreas Kemnade wrote:
> > On Wed, 13 May 2026 16:10:16 +0300
> > Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> wrote:
> >   
> >> Update comment about the number of lanes.
> >>
> >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
> >> ---
> >>   drivers/gpu/drm/bridge/tc358762.c | 9 ++++++++-
> >>   1 file changed, 8 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c
> >> index 7840ab3454f6..c5734c4df440 100644
> >> --- a/drivers/gpu/drm/bridge/tc358762.c
> >> +++ b/drivers/gpu/drm/bridge/tc358762.c
> >> @@ -306,7 +306,14 @@ static int tc358762_probe(struct mipi_dsi_device *dsi)
> >>   	ctx->dev = dev;
> >>   	ctx->pre_enabled = false;
> >>   
> >> -	/* TODO: Find out how to get dual-lane mode working */
> >> +	/*
> >> +	 * When using DSI clk for pixel clock (only mode supported in the driver),
> >> +	 * the pclk is derived directly from the DSI byteclk via simple divider,
> >> +	 * which is either 2 or 3.
> >> +	 * The required divider can be calculated with bitspp / 8 / nlanes. Thus,
> >> +	 * for RGB888, only nlanes = 1 works as nlanes = 2 would require divider
> >> +	 * of 1.5.
> >> +	 */
> >>   	dsi->lanes = 1;
> >>   	dsi->format = MIPI_DSI_FMT_RGB888;
> >>   	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> >>  
> > wondering: I am using lanes = 2 and RGB888. But I need to write something to
> > SYSPLL3 register. Which somehow is sensitive to write to.... Do you have any
> information about that register?  
> If you have an external refclk, then you can use the tc358762 pll to 
> generate the clock, which I guess you are using. SYSPLL3 configures some 
> parts of the PLL, and the doc says the write to SYSPLL3 must be the last 
> in the sequence.
>
Thanks for that explaination. Your comment in the code is really helpful.

I have anly a 22 page datasheet and I know only that the reference clock 
can be 6-40Mhz from that datasheet and the pixclock is 41600 according to
drm_display_mode struct.
I know the value which works is 0xB8640000.

I am asking all this since I want to upstream the display support for the
Epson Movero BT-200. The vendor kernel is 3.0. It is an old-style omapfb
display driver there. I converted it to a modern drm panel driver
with integrated bridge handling and now I am investingating how to use the
bridge driver together with a separate panel driver.

The clean way would be to define the input clock, and add code to 
calculate pll parameters. But without information, probably the
best way is to adjust magic numbers based on
if (of_machine_is_compatible())

Regards,
Andreas