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[80.230.85.71]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4923ff821aasm417318305e9.12.2026.06.23.11.37.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2026 11:37:35 -0700 (PDT) Date: Tue, 23 Jun 2026 14:37:32 -0400 From: "Michael S. Tsirkin" To: Peter Maydell Cc: Alejandro Jimenez , qemu-devel@nongnu.org, sarunkod@amd.com, pbonzini@redhat.com, richard.henderson@linaro.org Subject: Re: [PATCH 2/2] amd_iommu: Fully initialize XT interrupt message state Message-ID: <20260623143614-mutt-send-email-mst@kernel.org> References: <20260623005813.984238-1-alejandro.j.jimenez@oracle.com> <20260623005813.984238-3-alejandro.j.jimenez@oracle.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Jun 23, 2026 at 09:44:10AM +0100, Peter Maydell wrote: > On Tue, 23 Jun 2026 at 01:58, Alejandro Jimenez > wrote: > > > > When IOMMU x2APIC interrupts generation (IntCapXTEn) is enabled, > > amdvi_build_xt_msi_msg() builds an MSI message using the relevant values in > > the XT IOMMU General Interrupt Control Register. > > > > Initialize the local X86IOMMUIrq structure with zero for all fields. This > > ensures that X86IOMMUIrq fields not set in the XT register (e.g. > > msi_addr_last_bits) are initialized before x86_iommu_irq_to_msi_message() > > consumes them. > > > > Remove the redundant 'struct' keyword in X86IOMMUIrq irq declaration. > > > > CID: 1660056 > > Fixes: cf0210df65aa ("amd_iommu: Generate XT interrupts when xt support is enabled") > > Reported-by: Peter Maydell > > Suggested-by: Peter Maydell > > Signed-off-by: Alejandro Jimenez > > --- > > hw/i386/amd_iommu.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > > index 0d273fd33d..9005dc7aab 100644 > > --- a/hw/i386/amd_iommu.c > > +++ b/hw/i386/amd_iommu.c > > @@ -195,7 +195,7 @@ static void amdvi_assign_andq(AMDVIState *s, hwaddr addr, uint64_t val) > > static void amdvi_build_xt_msi_msg(AMDVIState *s, MSIMessage *msg) > > { > > union mmio_xt_intr xt_reg; > > - struct X86IOMMUIrq irq; > > + X86IOMMUIrq irq = { 0 }; Why don't we just initialize everything at the declaration site? union mmio_xt_intr xt_reg = { .val = ... }; X86IOMMUIrq irq = { .... }; > This is fine for the Coverity problem, but you do also need to > get rid of the bitfield-union as a separate issue. Ideal task for AI actually. > Reviewed-by: Peter Maydell > > thanks > -- PMM