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From: sashiko-bot@kernel.org
To: "Grégoire Layet" <gregoire.layet@9elements.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v3 7/7] ARM: dts: aspeed: g6: add aspeed,vuart-over-pci prop to vuart3 and 4
Date: Tue, 23 Jun 2026 14:44:30 +0000	[thread overview]
Message-ID: <20260623144430.7CE281F000E9@smtp.kernel.org> (raw)
In-Reply-To: <86fc0b2a105a16ceb301ba53fadd096877455bb8.1782224060.git.gregoire.layet@9elements.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Low] Adding `aspeed,vuart-over-pci` to nodes with multiple compatible strings violates the `const` constraint in the YAML binding, causing a schema validation failure.

Pre-existing issues:
- [High] Probe error paths fail to unregister the 8250 port and remove the sysfs group, resulting in a use-after-free of the devm-allocated driver state and resource leaks.
--

commit 3ce60a66a65e6d307209da21c88e6e5c758ddf74
Author: Grégoire Layet <gregoire.layet@9elements.com>
Date:   Tue Jun 23 14:25:45 2026 +0000

    ARM: dts: aspeed: g6: add aspeed,vuart-over-pci prop to vuart3 and 4
    
    The VUART 3 and 4 are VUART over PCI.
    This flag indicates this information.

> diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> index 5ff52697e8bb4..b33468288d4a5 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> @@ -714,6 +714,7 @@ vuart3: serial@1e787800 {
>  				interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
>  				clocks = <&syscon ASPEED_CLK_APB2>;
>  				no-loopback-test;
> +				aspeed,vuart-over-pci;

[Severity: Low]
Does adding this property cause a device tree schema validation failure?

Looking at Documentation/devicetree/bindings/serial/8250.yaml, the schema
restricts the compatible property to a single string when
aspeed,vuart-over-pci is present:

        compatible:
          const: aspeed,ast2600-vuart

Since the vuart3 node uses multiple compatible strings
("aspeed,ast2600-vuart", "aspeed,ast2500-vuart"), does this violate the
constraint and cause dtbs_check to fail?

[Severity: High]
This isn't a bug introduced by this patch, but adding this property appears
to trigger a pre-existing resource leak and use-after-free in the driver's
error path.

In drivers/tty/serial/8250/8250_aspeed_vuart.c, if
aspeed_ast2600_vuart_over_pci_set_enabled() fails during
aspeed_vuart_probe(), the function returns directly:

        rc = aspeed_ast2600_vuart_over_pci_set_enabled(pdev);
        if (rc) {
                dev_err(dev, "could not enable VUART over PCI\n");
                return rc;
        }

Does this bypass calling serial8250_unregister_port() and
sysfs_remove_group() after a successful serial8250_register_8250_port()?
Since the devm-allocated driver state is freed on probe failure, does the
UART core retain a registered port pointing to freed memory?

>  				status = "disabled";
>  			};

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782224059.git.gregoire.layet@9elements.com?part=7

      reply	other threads:[~2026-06-23 14:44 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-02 14:42 [PATCH v1 0/2] soc: aspeed: Add BMC and host driver for PCIe BMC device Grégoire Layet
2026-06-02 14:42 ` [PATCH v1 1/2] soc: aspeed: add BMC-side PCIe BMC device driver Grégoire Layet
2026-06-02 14:42 ` [PATCH v1 2/2] soc: aspeed: add host-side " Grégoire Layet
2026-06-02 15:49   ` Andrew Lunn
2026-06-03 13:43     ` Grégoire Layet
2026-06-03 14:30       ` Andrew Lunn
2026-06-04  0:44         ` Andrew Jeffery
2026-06-04  0:46       ` Andrew Jeffery
2026-06-08 14:51 ` [PATCH v2 0/2] soc: aspeed: Add BMC and host driver for PCIe BMC device Grégoire Layet
2026-06-08 14:51   ` [PATCH v2 1/2] soc: aspeed: add BMC-side PCIe BMC device driver Grégoire Layet
2026-06-10 12:33     ` Andrew Jeffery
2026-06-11  8:40       ` Grégoire Layet
2026-06-12  9:21         ` Grégoire Layet
2026-06-16  0:16           ` Andrew Jeffery
2026-06-17  6:40             ` Grégoire Layet
2026-06-18  0:58               ` Andrew Jeffery
2026-06-08 14:51   ` [PATCH v2 2/2] soc: aspeed: add host-side " Grégoire Layet
2026-06-10 12:51     ` Andrew Jeffery
2026-06-11  8:41       ` Grégoire Layet
2026-06-08 18:05   ` [PATCH v2 0/2] soc: aspeed: Add BMC and host driver for PCIe BMC device Andrew Lunn
2026-06-09 13:34     ` Grégoire Layet
2026-06-23 14:25   ` [PATCH v3 0/7] " Grégoire Layet
2026-06-23 14:25     ` [PATCH v3 1/7] dt-bindings: serial: 8250: aspeed: add compatible string for ast2600 Grégoire Layet
2026-06-23 14:35       ` sashiko-bot
2026-06-23 14:25     ` [PATCH v3 2/7] dt-bindings: serial: 8250: aspeed: add aspeed,vuart-over-pci bool prop Grégoire Layet
2026-06-23 14:38       ` sashiko-bot
2026-06-23 14:25     ` [PATCH v3 3/7] serial: 8250_aspeed_vuart: add aspeed,ast2600-vuart compatible string Grégoire Layet
2026-06-23 14:41       ` sashiko-bot
2026-06-23 14:25     ` [PATCH v3 4/7] serial: 8250_aspeed_vuart: add VUART over PCI Grégoire Layet
2026-06-23 14:41       ` sashiko-bot
2026-06-23 14:25     ` [PATCH v3 5/7] soc: aspeed: add host-side PCIe BMC device driver Grégoire Layet
2026-06-23 14:40       ` sashiko-bot
2026-06-23 14:25     ` [PATCH v3 6/7] ARM: dts: aspeed: g6: Change vuart compatible string for ast2600 Grégoire Layet
2026-06-23 14:42       ` sashiko-bot
2026-06-23 14:25     ` [PATCH v3 7/7] ARM: dts: aspeed: g6: add aspeed,vuart-over-pci prop to vuart3 and 4 Grégoire Layet
2026-06-23 14:44       ` sashiko-bot [this message]

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