Re: [PATCH v2 2/2] arm64: dts: socfpga: agilex72: Add initial device tree

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Missing VGIC maintenance interrupt breaks KVM virtualization support.
- [Medium] Invalid properties in static `reserved-memory` nodes (ATF and service buffers).
- [Medium] Missing CPU capacity properties for heterogeneous ARMv9 scheduling.
--

commit aab0b211863fe0abf5dfd65b45d11637ecf3a3d5
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: agilex72: Add initial device tree

This commit introduces the initial device tree support for the Intel
SoCFPGA Agilex72 platform, including the SoC DTSI and the SoCDK board
DTS.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
> new file mode 100644
> index 0000000000000..2a4ad4130f37e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
> @@ -0,0 +1,128 @@
[ ... ]
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		atf_reserved: atf@80000000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x0 0x80000000 0x0 0x100000>;
> +			alignment = <0x1000>;
> +			no-map;
> +		};
> +
> +		service_reserved: svcbuffer@80100000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x0 0x80100000 0x0 0xf00000>;
> +			alignment = <0x1000>;
> +			no-map;
> +		};
> +	};

[Severity: Medium]
Is it intentional to expose the Arm Trusted Firmware secure memory region
as a shared DMA pool? The compatible = "shared-dma-pool" property here could
expose secure EL3 memory as a Linux DMA pool, which could trigger a fatal
secure monitor abort if a driver attempts to attach and access it.

Also, both the atf_reserved and service_reserved nodes define a static
physical address using the reg property, but they also include the alignment
property. Does this violate the devicetree schema? The reserved-memory.yaml
schema dictates that alignment is strictly for dynamically placed allocations
and is mutually exclusive with reg.

[ ... ]
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a520";
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			reg = <0x0>;
> +		};
[ ... ]
> +		cpu2: cpu@200 {
> +			compatible = "arm,cortex-a720";
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			reg = <0x200>;
> +		};

[Severity: Medium]
Since the Agilex72 features a heterogeneous cluster with Cortex-A520
and Cortex-A720 cores, does this cpus node need capacity-dmips-mhz
properties? 

Without these properties or an active OPP table, the Energy Aware Scheduling
(EAS) subsystem cannot discover the relative compute capacities, and might
assume all cores are identical. This could cause heavy workloads to be
scheduled suboptimally on the slower A520 cores.

[ ... ]
> +	intc: interrupt-controller@7000000 {
> +		compatible = "arm,gic-v3";
> +		reg = <0x0 0x7000000 0x0 0x10000>,
> +		      <0x0 0x7080000 0x0 0x100000>;
> +		ranges;
> +		#interrupt-cells = <3>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		interrupt-controller;

[Severity: High]
Is the VGIC maintenance interrupt missing from this node? 

KVM relies on this interrupt (typically GIC_PPI 9) to populate gic_v3_kvm_info
during the GICv3 driver initialization in drivers/irqchip/irq-gic-v3.c.
Without it, the driver skips VGIC setup, which leaves hardware virtualization
support broken on this platform.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260624055644.7508-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2