[PATCH 0/1 v4] drm/xe: Wait for HW clearance before issuing the next TLB inval.

[fei.yang@intel.com]

From: Fei Yang <fei.yang@intel.com>

Attempt again after validating this in the internal tree for a while.
I hope this time it will pass the CI.
I knew Matt Brost wanted to have a GAM port layer for the mmio access,
but not sure if it worth the effort if the only usage is for MMIO-based
TLB invalidation.


Fei Yang (1):
  drm/xe: Wait for HW clearance before issuing the next TLB inval.

 drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 70 +++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

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2.43.0