Re: [PATCH v3 2/5] dmaengine: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The patch correctly bypasses the XOR byte-lane adjustment for 8-bit registers on MCF eDMA via the FSL_EDMA_DRV_MCF flag, but fails to apply the same bypass for 16-bit registers written via edma_writew(). This will corrupt TCD 16-bit register writes on ColdFire platforms.
--

commit e23a155133dba0ca56d6eea575c63bb35a8ef9ab
Author: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>

dmaengine: fsl-edma: Add FSL_EDMA_DRV_MCF flag for ColdFire eDMA

This commit adds a new flag FSL_EDMA_DRV_MCF for the ColdFire eDMA driver to
bypass the XOR byte-lane adjustment for 8-bit registers, ensuring writes
target the correct documented addresses.

> diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
> index abc8f78055156..64b5375272917 100644
> --- a/drivers/dma/fsl-edma-common.h
> +++ b/drivers/dma/fsl-edma-common.h

[ ... ]

> @@ -419,7 +421,8 @@ static inline void edma_writeb(struct fsl_edma_engine *edma,
>  			       u8 val, void __iomem *addr)
>  {
>  	/* swap the reg offset for these in big-endian mode */
> -	if (edma->big_endian)
> +	/* MCF eDMA has different register layout, no XOR needed */
> +	if (edma->big_endian && !(edma->drvdata->flags & FSL_EDMA_DRV_MCF))
>  		iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
>  	else
>  		iowrite8(val, addr);

[Severity: High]
This isn't a bug introduced by this patch, but should edma_writew() be updated
to bypass the address adjustment as well?

Looking at edma_writew() right below this function, it performs 16-bit writes
and unconditionally applies the ^ 0x2 XOR offset adjustment for big-endian
controllers:

drivers/dma/fsl-edma-common.h:edma_writew() {
	/* swap the reg offset for these in big-endian mode */
	if (edma->big_endian)
		iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
    ...
}

Without checking FSL_EDMA_DRV_MCF here, wouldn't writing 16-bit TCD registers
on native ColdFire platforms still apply the ^ 0x2 offset and incorrectly swap
registers like soff and attr?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260625-b4-edma-dmaengine-v3-0-44be00ace37d@yoseli.org?part=2