From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D2FF372EC5 for ; Fri, 26 Jun 2026 07:48:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782460111; cv=none; b=RAOmZN9PG8B9jmwHwer368OCe6vmnD+qpW3W/Gf6JR8NLT3R2/NAxJt22HT0vLxQm98W3TY15MzQIuDIK74WUN5t4MRT1CJMzHF4mQEoz/MADeUXVMFX5iOdWu9HUzkLMb7RslAltbj1S02V0dXAjbxLSQ6OBP5R1Vzz7QhYNQA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782460111; c=relaxed/simple; bh=KMmc0oxXQiPSXf13gKsegHINnJ3l4/k6oBvr9bUNawA=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=l2i4FEZwMrozTD56Fw/6qWQqV+/pu5Y8sfdDbtygExxDuZqjKDyn9NWZgy6LRl28fRq+0x4R5vRH/FxgGtR3QhhjuncuI+z9p48ekgu+JdhF/hU0sW81H45nrQgXEaQvS9DCZp8EPJH3MEKJYbbl7PBYvF7uYRERLk1RS/nvUfg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=JAwBeFVf; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="JAwBeFVf" X-UUID: 6875625a713311f18dc8c9802ae25ab1-20260626 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=1aJai2EacD3fT+kMpiw5eHMwfJpEII/nsylCRovDvHU=; b=JAwBeFVfpyk/oiRefL/ZvMmw2VqbymGgzQGB9Hm2JcrMbiHppkNNIJxyJi8UMbf6rRwZHCP8aDny5XEtSSjFbBbolY+RY2ZWp2dXnXa4JvmemyuyIx1hdHvY4wDpjaY5ZPbaMTg0EzfJSdp4punV7xiCuzh6KSeKL0AET05z3O4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.17,REQID:b35d236e-e602-4869-94cc-473f73f219b1,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:d497b38,CLOUDID:02c5dffc-4e5b-4880-a751-e09c9abb260d,B ulkID:nil,BulkQuantity:0,SF:102|123|136|836|865|888|898,TC:-5,Content:0|15 |50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI:0,O SA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 6875625a713311f18dc8c9802ae25ab1-20260626 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 831688034; Fri, 26 Jun 2026 15:48:23 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 26 Jun 2026 15:48:22 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 26 Jun 2026 15:48:22 +0800 From: To: CC: , , , , , , , , , , , , , Subject: [PATCH v1 0/2] reset: mediatek: add syscon-based reset controller Date: Fri, 26 Jun 2026 15:46:07 +0800 Message-ID: <20260626074820.2537772-1-peter.wang@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N From: Peter Wang This series adds support for a MediaTek SYSCON-based reset controller that manages reset lines through memory-mapped registers within a syscon MFD block. Peter Wang (2): Documentation: dt: reset: add mediatek,syscon-reset binding reset: mediatek: add syscon-based reset controller driver .../bindings/reset/mediatek,syscon-reset.yaml | 93 +++++++ drivers/reset/Kconfig | 10 + drivers/reset/Makefile | 1 + drivers/reset/reset-mediatek-syscon.c | 230 ++++++++++++++++++ 4 files changed, 334 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek,syscon-reset.yaml create mode 100644 drivers/reset/reset-mediatek-syscon.c -- 2.45.2