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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-492690a1a85sm101588975e9.15.2026.06.26.01.06.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2026 01:06:16 -0700 (PDT) Date: Fri, 26 Jun 2026 09:06:15 +0100 From: David Laight To: Michal Pecio Cc: Xincheng Zhang , cyrozap@gmail.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, mathias.nyman@intel.com Subject: Re: [PATCH] usb: xhci-pci: Disable 64-bit DMA for VIA VL805 Message-ID: <20260626090615.616666b4@pumpkin> In-Reply-To: <20260625191852.0a8d511c.michal.pecio@gmail.com> References: <20260623121847.53749028.michal.pecio@gmail.com> <20260624070612.337013-1-zhangxincheng@ultrarisc.com> <20260625020421.2e577a94.michal.pecio@gmail.com> <178235378952.3114334.15752812276771065417.b4-reply@b4> <20260625191852.0a8d511c.michal.pecio@gmail.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 25 Jun 2026 19:18:52 +0200 Michal Pecio wrote: ... > Right, your addresses barely exceed the 36 bit limit. And I found why > my chip behaved differently - 40 bit DMA was a firmware upgrade. > > After downgrading my controller from 00013704 to 00013600 it truncates > addresses to 36 bits and fails like yours. And it's a pretty nasty bug, > because some of those accesses are writes to scratchpad buffers, so > without IOMMU the chip corrupts unrelated memory below 64GB. > > You can check your FW version with this one-liner: > lspci -d 1106:3483 -xxx | awk '/^50:/ { print "VL805 FW version: " $5 $4 $3 $2 }' > > More about VL805 firmwares: > https://github.com/jpmorrison/VL805 > > One could ask whether 36 bits is low enough for all VL805, but I think > it is because the bug is hard not to notice and nobody ever reported it > on systems with less than 64 GB of RAM, even though 16 or 32 GB without > IOMMU was a common option in DDR3 generation PCs, which is also about > the era when this controller was introduced. 36 bits is just enough to support 32bit x86 with PAE. Seems very short sighted. IIRC xhci has a quite restrictive limit on address boundaries so supporting larger addresses is just latches - there is no need for a 64bit counter. Can you do a read-back of one of the control registers that contains an address - if you are lucky the high bits will return zero. That might let the generic code enforce a limit. -- David > > Regards, > Michal >