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Peter Anvin" , "Joerg Roedel (AMD)" , Borislav Petkov , Dave Hansen , Ingo Molnar , Paolo Bonzini , "Robin Murphy" , Sairaj Kodilkar , "Sean Christopherson" , Suravee Suthikulpanit , Thomas Gleixner , "Vasant Hegde" , Will Deacon , , , , Subject: [RFC PATCH 2/5] iommu/amd: Configure IRTE to use the GAPPI for posted interrupts Date: Fri, 26 Jun 2026 16:29:03 +0530 Message-ID: <20260626105906.14577-3-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260626105906.14577-1-sarunkod@amd.com> References: <20260626105906.14577-1-sarunkod@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000143:EE_|SA0PR12MB4381:EE_ X-MS-Office365-Filtering-Correlation-Id: ccade098-5f09-4d48-3548-08ded3721a7a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|7416014|376014|82310400026|23010399003|56012099006|11063799006|18002099003|22082099003|921020; X-Microsoft-Antispam-Message-Info: D6lG/Z5kR3B4Wo3X/79nXa9HwZ4PDk00SY6YO/Jio/ANjJtmUgWP5BRAfQfKBnvraqlCMRQXKEJn+O6OEXVV7rZuLLZ98/CrNhueQD+klNfjJF5rvGWAV24xnTCnF23cLkh03W2SXuiCjcqH7rC+lrQt8OBENckG4zFIHJo3vJnrpt1y7eDGfsrjB59t0pgMgMELviBckwIATqQxC4oib44XN+yGGSimMo7scojzbsc6jJyFmGowB9/uqiwroflUxOSIW40Lty+TD97gVVtbLnOQxWxSgG0Fgt71ijDMNlMrof8zzrdTn1l27HCrVTaFlFrFct94zv07xNP8rzhA+7SjR2jc35Vo7sYbQtiDGfoASMgysn4Kn4EWZP/G9h4S8+sqv6iQL0YDg75FIGkRpMy4Rwc3ZYuSJFGNPOnuftok/F8XU2f6ouZCs2G1bGdzjhJNqIykI5ewQNs1Xphl1udivTqf01fs72IhXHazPOipGgBo6qdF4sVI62+6oLGc1xh/0k6OG0Nac0Ej0r2IMJxZ0X/1do0zhNBYQDbLhC9xEzk8hBNz+G0d6odqM2C2rbZc1GMYPMK1vtfUAx+bCBqEcDkDssoH03tOeUlKIhRELdGDjVhFVK27d5GkbpvqzeQ6AMqOTUC6317Snd2XUxqT5el52f8BZNB2Tq0v6lGVitamCkNfV8NNKIMjHIooizmUb2hdh8RsA9xY9ELxx61ZGr6xrPC94XsiNf8mPF8a5B+9xMrqKHg+cN6dfic5 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(7416014)(376014)(82310400026)(23010399003)(56012099006)(11063799006)(18002099003)(22082099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GZrJseatxhIticRyyxdfUrYdwS17z7GFSXW0xjELmzEWQ3sn0jXJmYqaDpJSBExVUV9rCKXhYzZJo0cUv24C9DP/72TdKhqr24uFfsOEmz6x5P+KCThx1azbb0ZNLBl9n0Njks8ERje/asP6WhRq6N8vveRLiUriTmi/Ab7riqmu2hvP6hJEukZbPd0BQg2JDEjJcsJQbTYZuPlxbj9mePI9iK+qcTh2H1qqTZkQOuh3dAxLFqscCIHTIJs/9pGlrIwwfUuAdBKauGrfcmYgaw+xDYTENgVw8UHLANqzyFwYdybbqY6Y/S4LOjjMfhBYjuFZyB5j8gIaaxInKojqL/0mhr5B/1V+GCsNSBplixswsMcB31Ijj/+xCNaq1We0CuIbH6G/w5XchY0gOJC9uYDr3NJmWsC9R8rv1fUYjCv3Akr0c75PjrDb/SYJvCYs X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2026 11:00:15.6589 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ccade098-5f09-4d48-3548-08ded3721a7a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000143.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4381 When GAPPI is enabled, a guest-mode IRTE with is_run clear delivers a GAPPI interrupt to the physical APIC ID in the IRTE destination fields, with the wake vector carried in ga_tag. Program the guest-activated IRTE accordingly. Reuse the POSTED_INTR_WAKEUP_VECTOR for gappi which is already reserved for posted interrupt wakeup handler on x86 and is handled by IDTE entry sysvec_kvm_posted_intr_wakeup_ipi. Intel VMX already uses same vector for the wakeup case. Signed-off-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 5 +++++ drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/amd_iommu_types.h | 4 +++- drivers/iommu/amd/init.c | 3 +++ drivers/iommu/amd/iommu.c | 21 +++++++++++++++++---- include/linux/amd-iommu.h | 1 + 6 files changed, 30 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 7862b13c5409..b666efb5d91c 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -955,6 +955,11 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, } else { posted_intr = !!(entry & AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR); pi_data.flags = posted_intr << AMD_IOMMU_FLAG_POSTED_INTR_SHIFT; + /* GAPPI is disabled at this point (amd_iommu_gappi is + * enabled in the following patches) hence keep the + * apicid as 0. + */ + pi_data.apicid = 0; } ret = irq_set_vcpu_affinity(host_irq, &pi_data); diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 834d8fabfba3..044179cab12e 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -41,6 +41,7 @@ int amd_iommu_enable(void); void amd_iommu_disable(void); int amd_iommu_reenable(int mode); int amd_iommu_enable_faulting(unsigned int cpu); +extern bool amd_iommu_gappi; extern int amd_iommu_guest_ir; extern enum protection_domain_mode amd_iommu_pgtable; extern int amd_iommu_gpt_level; diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index f9f718087893..26d7a9796e64 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -113,6 +113,7 @@ /* Extended Feature 2 Bits */ #define FEATURE_SEVSNPIO_SUP BIT_ULL(1) #define FEATURE_GCR3TRPMODE BIT_ULL(3) +#define FEATURE_GAPPIDISSUP BIT_ULL(4) #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5) #define FEATURE_SNPAVICSUP_GAM(x) \ (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1) @@ -1004,7 +1005,8 @@ union irte_ga_lo { no_fault : 1, /* ------ */ ga_log_intr : 1, - rsvd1 : 3, + rsvd1 : 2, + gappi_dis : 1, is_run : 1, /* ------ */ guest_mode : 1, diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 3bdb380d23e9..2e1889f8a9e4 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -160,6 +160,9 @@ u8 amd_iommu_hpt_level; /* Guest page table level */ int amd_iommu_gpt_level = PAGE_MODE_4_LEVEL; +bool amd_iommu_gappi; +EXPORT_SYMBOL(amd_iommu_gappi); + int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 76f0e469490e..4690cecc9aa7 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3969,9 +3969,18 @@ static void __amd_iommu_update_ga(struct irte_ga *entry, int apicid, int flags) entry->lo.fields_vapic.is_run = true; entry->lo.fields_vapic.ga_log_intr = false; } else { - entry->lo.fields_vapic.is_run = false; - entry->lo.fields_vapic.ga_log_intr = !!(flags & - AMD_IOMMU_FLAG_POSTED_INTR); + bool posted_intr = !!(flags & AMD_IOMMU_FLAG_POSTED_INTR); + if (amd_iommu_gappi) { + entry->lo.fields_vapic.gappi_dis = !posted_intr && + check_feature2(FEATURE_GAPPIDISSUP); + entry->lo.fields_vapic.is_run = false; + entry->lo.fields_vapic.destination = + APICID_TO_IRTE_DEST_LO(apicid); + entry->hi.fields.destination = APICID_TO_IRTE_DEST_HI(apicid); + } else { + entry->lo.fields_vapic.is_run = false; + entry->lo.fields_vapic.ga_log_intr = posted_intr; + } } } @@ -4034,7 +4043,11 @@ int amd_iommu_activate_guest_mode(void *data, int apicid, int flags) entry->lo.fields_vapic.guest_mode = 1; entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr; entry->hi.fields.vector = ir_data->ga_vector; - entry->lo.fields_vapic.ga_tag = ir_data->ga_tag; + + if (amd_iommu_gappi) + entry->lo.fields_vapic.ga_tag = POSTED_INTR_WAKEUP_VECTOR; + else + entry->lo.fields_vapic.ga_tag = ir_data->ga_tag; __amd_iommu_update_ga(entry, apicid, flags); diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index 3dd9074e5967..87e76f617ea1 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -82,4 +82,5 @@ static inline bool amd_iommu_sev_tio_supported(void) { return false; } #define AMD_IOMMU_FLAG_POSTED_INTR_SHIFT 1 #define AMD_IOMMU_FLAG_POSTED_INTR BIT(1) +extern bool amd_iommu_gappi; #endif /* _ASM_X86_AMD_IOMMU_H */ -- 2.34.1