From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 207E83A4F23 for ; Mon, 29 Jun 2026 06:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782715207; cv=none; b=c9/eIsTMfYgOy4Xyory3XIy6B+1wDKZwXAEqTMJ0b9xOdfxpj9yO6eSHZ4ASkMA19wfDoVVcGCVWvRaidJgBYorgrvTlMfzlEBZNvQ5FMcD/HO/JrQv62Qm5UdPvLgkpk5dprEmqg1GBzLLDK4tACQBSxCdq088MmOYLgnfsL9U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782715207; c=relaxed/simple; bh=UI6bznI2xdxQ6tgpoU8lUfCLVF3L1C7/9kKG3ekTuIM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oF112K719TKzbS4XcIaDwYRT0FgT82ssjFjcBKNbVPORGyJ7Dp2LiWhFUc2ci6DK93ewBgp5vRfut5WiFhzH6KkD80PMRaslmRLMTEvlqoYQ2S2e78frEW2ypdx5bJi+K5WrQtMps/TeZdkViZloJBNURsM6z0amNXHfrsC3j7M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=gBViGYJS; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=gBViGYJS; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="gBViGYJS"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="gBViGYJS" Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 34C2E70EC1; Mon, 29 Jun 2026 06:40:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1782715203; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=novGEUYDQFJs4wPwpcnjByYzQUJMgfjvSdSg5bgUj00=; b=gBViGYJSnrFZ6sx2KcfMJ0KfV2lggQPWb0scWJUgrFjWhJiJD0+KWHzYmqwWC4ZsjfcxAA eZucWZChOQOBMyyueneHkzh54wE92AzsLM15bfVCVXhRRIjfrzlvTAprHTzL72WyD1X1ME Kr1ZSWnGP9N6WPIWcK4yKEhXxJc1/VQ= Authentication-Results: smtp-out1.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1782715203; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=novGEUYDQFJs4wPwpcnjByYzQUJMgfjvSdSg5bgUj00=; b=gBViGYJSnrFZ6sx2KcfMJ0KfV2lggQPWb0scWJUgrFjWhJiJD0+KWHzYmqwWC4ZsjfcxAA eZucWZChOQOBMyyueneHkzh54wE92AzsLM15bfVCVXhRRIjfrzlvTAprHTzL72WyD1X1ME Kr1ZSWnGP9N6WPIWcK4yKEhXxJc1/VQ= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id E7785779A8; Mon, 29 Jun 2026 06:40:02 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id n7wMN0ITQmodMgAAD6G6ig (envelope-from ); Mon, 29 Jun 2026 06:40:02 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH 3/5] x86/msr: Switch users of native_rdmsr() to native_rdmsrq() Date: Mon, 29 Jun 2026 08:39:41 +0200 Message-ID: <20260629063943.3641266-4-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629063943.3641266-1-jgross@suse.com> References: <20260629063943.3641266-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Flag: NO X-Spam-Score: -2.80 X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MIME_TRACE(0.00)[0:+]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCVD_TLS_ALL(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; RCVD_COUNT_TWO(0.00)[2]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email,suse.com:mid] X-Spam-Level: Switch all users of native_rdmsr() to native_rdmsrq() in order to prepare removal of native_rdmsr(). Signed-off-by: Juergen Gross --- arch/x86/include/asm/microcode.h | 6 +----- arch/x86/kernel/cpu/microcode/amd.c | 4 ++-- arch/x86/kernel/cpu/microcode/core.c | 4 ++-- arch/x86/kernel/cpu/microcode/intel.c | 6 +++--- 4 files changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 9cd136d4515c..898db0a32888 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -66,17 +66,13 @@ extern u32 intel_get_platform_id(void); static inline u32 intel_get_microcode_revision(void) { - u32 rev, dummy; - native_wrmsrq(MSR_IA32_UCODE_REV, 0); /* As documented in the SDM: Do a CPUID 1 here */ native_cpuid_eax(1); /* get the current revision from MSR 0x8B */ - native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); - - return rev; + return native_rdmsrq(MSR_IA32_UCODE_REV) >> 32; } #endif /* !CONFIG_CPU_SUP_INTEL */ diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 531dfb771c8b..6e24d9b7053f 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -316,7 +316,7 @@ static union cpuid_1_eax ucode_rev_to_cpuid(unsigned int val) static u32 get_patch_level(void) { - u32 rev, dummy __always_unused; + u32 rev; if (IS_ENABLED(CONFIG_MICROCODE_DBG) && x86_hypervisor_present) { int cpu = smp_processor_id(); @@ -333,7 +333,7 @@ static u32 get_patch_level(void) return microcode_rev[cpu]; } - native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); + rev = native_rdmsrq(MSR_AMD64_PATCH_LEVEL); if (!rev) { if (x86_family(bsp_cpuid_1_eax) < 0x17) return rev; diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 0dd0c7241c57..ea696a202c31 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -94,13 +94,13 @@ struct early_load_data early_data; */ static bool amd_check_current_patch_level(void) { - u32 lvl, dummy, i; + u32 lvl, i; u32 *levels; if (x86_cpuid_vendor() != X86_VENDOR_AMD) return false; - native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy); + lvl = native_rdmsrq(MSR_AMD64_PATCH_LEVEL); levels = final_levels; diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 4d860fea5cc8..d539671ecf3b 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -137,7 +137,7 @@ static u32 intel_cpuid_vfm(void) u32 intel_get_platform_id(void) { - unsigned int val[2]; + u64 val; if (x86_hypervisor_present) return 0; @@ -152,9 +152,9 @@ u32 intel_get_platform_id(void) return 0; /* get processor flags from MSR 0x17 */ - native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); + val = native_rdmsrq(MSR_IA32_PLATFORM_ID); - return (val[1] >> 18) & 7; + return (val >> 50) & 7; } void intel_collect_cpu_info(struct cpu_signature *sig) -- 2.54.0