From: Dinh Nguyen <dinguyen@kernel.org>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org
Cc: dinguyen@kernel.org, devicetree@vger.kernel.org,
muhammad.nazim.amirul.nazle.asmade@altera.com
Subject: [PATCHv2 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2
Date: Mon, 29 Jun 2026 06:48:18 -0500 [thread overview]
Message-ID: <20260629114818.1746410-2-dinguyen@kernel.org> (raw)
In-Reply-To: <20260629114818.1746410-1-dinguyen@kernel.org>
Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue
pairs.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: no changes
---
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 72 +++++++++++++++++--
1 file changed, 68 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 2096decb5655..f54767d1526e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -702,8 +702,40 @@ gmac1: ethernet@10820000 {
compatible = "altr,socfpga-stmmac-agilex5",
"snps,dwxgmac-2.10";
reg = <0x10820000 0x3500>;
- interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0",
+ "tx-queue-1",
+ "tx-queue-2",
+ "tx-queue-3",
+ "tx-queue-4",
+ "tx-queue-5",
+ "tx-queue-6",
+ "tx-queue-7",
+ "rx-queue-0",
+ "rx-queue-1",
+ "rx-queue-2",
+ "rx-queue-3",
+ "rx-queue-4",
+ "rx-queue-5",
+ "rx-queue-6",
+ "rx-queue-7";
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
@@ -816,8 +848,40 @@ gmac2: ethernet@10830000 {
compatible = "altr,socfpga-stmmac-agilex5",
"snps,dwxgmac-2.10";
reg = <0x10830000 0x3500>;
- interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0",
+ "tx-queue-1",
+ "tx-queue-2",
+ "tx-queue-3",
+ "tx-queue-4",
+ "tx-queue-5",
+ "tx-queue-6",
+ "tx-queue-7",
+ "rx-queue-0",
+ "rx-queue-1",
+ "rx-queue-2",
+ "rx-queue-3",
+ "rx-queue-4",
+ "rx-queue-5",
+ "rx-queue-6",
+ "rx-queue-7";
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
--
2.42.0.411.g813d9a9188
next prev parent reply other threads:[~2026-06-29 11:48 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-29 11:48 [PATCHv2 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 Dinh Nguyen
2026-06-29 11:48 ` Dinh Nguyen [this message]
2026-06-29 12:01 ` [PATCHv2 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2 sashiko-bot
2026-06-29 12:10 ` [PATCHv2 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 sashiko-bot
2026-06-29 15:17 ` Conor Dooley
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