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[87.132.234.133]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4926c2954efsm219567015e9.2.2026.06.29.11.20.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2026 11:20:42 -0700 (PDT) From: Andreas Zdziarstek To: u-boot@lists.denx.de Cc: trini@konsulko.com, sjg@chromium.org, philipp.tomsich@vrull.eu, kever.yang@rock-chips.com, jonas@kwiboo.se, quentin.schulz@cherry.de, Andreas Zdziarstek Subject: [PATCH v3 1/3] rockchip: rk3568: make the WDT trigger a first global reset Date: Mon, 29 Jun 2026 20:20:10 +0200 Message-ID: <20260629182012.1508336-2-andreas.zdziarstek@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260629182012.1508336-1-andreas.zdziarstek@gmail.com> References: <20260629182012.1508336-1-andreas.zdziarstek@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Default is a second global reset which causes a system hang on a timeout in U-Boot. Access the register through the rk3568_cru struct to match how PX30 does it in arch_cpu_init(). Verified on the Hardkernel ODROID-M1S (RK3566): a watchdog timeout now cleanly reboots the board. Signed-off-by: Andreas Zdziarstek --- arch/arm/mach-rockchip/rk3568/rk3568.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 2b1eafee37c..8bed529a5c1 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -37,6 +38,9 @@ #define CPU_GRF_BASE 0xfdc30000 #define GRF_CORE_PVTPLL_CON0 (0x10) +#define CRU_BASE 0xfdd20000 +#define WDT_GLB_SRST_CTRL BIT(1) + /* PMU_GRF_GPIO0D_IOMUX_L */ enum { GPIO0D1_SHIFT = 4, @@ -117,6 +121,8 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { #ifdef CONFIG_XPL_BUILD + static struct rk3568_cru * const cru = (void *)CRU_BASE; + /* * When perform idle operation, corresponding clock can * be opened or gated automatically. @@ -145,6 +151,9 @@ int arch_cpu_init(void) /* Enable VO power domain for display */ writel((PMU_PD_VO_DWN_ENA << 16), PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON); + + /* Make WDT trigger a first global reset */ + setbits_le32(&cru->glb_rst_con, WDT_GLB_SRST_CTRL); #endif return 0; } -- 2.53.0