Re: [PATCH v3 01/11] dt-bindings: reserved-memory: Document Tegra VPR

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The examples section lacks a parent `reserved-memory` node defining `#address-cells = <2>` and `#size-cells = <2>`, causing `make dt_binding_check` to fail due to property length mismatches.
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commit 4ece5321c623dd3f99c7265c3f5b7ed31b2d2efe
Author: Thierry Reding <treding@nvidia.com>

dt-bindings: reserved-memory: Document Tegra VPR

This commit adds device tree binding documentation for the NVIDIA Tegra
Video Protection Region (VPR). It describes a protected memory region used
for DRM content, supporting both fixed and resizable variants.

> diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra-video-protection-region.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra-video-protection-region.yaml
> new file mode 100644
> index 0000000000000..1c524bae9ce32
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra-video-protection-region.yaml

[ ... ]

> +examples:
> +  - |
> +    /* resizable VPR */
> +    protected {
> +      compatible = "nvidia,tegra-video-protection-region";
> +
> +      size = <0x0 0x70000000>;
> +      alignment = <0x0 0x100000>;
> +      reusable;
> +    };
> +
> +  - |
> +    /* fixed VPR */
> +    protected@2a8000000 {
> +      compatible = "nvidia,tegra-video-protection-region";
> +
> +      /* fixed VPR */
> +      reg = <0x2 0xa8000000 0x0 0x70000000>;
> +      no-map;
> +    };

[Severity: Low]
Will this cause make dt_binding_check to fail due to property length
mismatches? 

The examples use 64-bit values for size, alignment, and reg, which require
2 cells. Without an explicit parent reserved-memory node defining
#address-cells = <2> and #size-cells = <2>, won't the tooling evaluate this
using default 1-cell constraints and report errors?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260701-tegra-vpr-v3-0-d80f7b871bb4@nvidia.com?part=1