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[80.230.68.31]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493c63ba97csm120590005e9.12.2026.07.03.03.23.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2026 03:23:52 -0700 (PDT) Date: Fri, 3 Jul 2026 06:23:49 -0400 From: "Michael S. Tsirkin" To: Peter Maydell Cc: qemu-devel@nongnu.org, Gerd Hoffmann , Pierrick Bouvier , Paolo Bonzini , Sergio Lopez , Song Gao , Bibo Mao , Jiaxun Yang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: Re: [PATCH 0/5] hw/nvram/fw_cfg: Document and tighten up register layouts Message-ID: <20260703062108-mutt-send-email-mst@kernel.org> References: <20260529174639.451353-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Jul 03, 2026 at 10:41:32AM +0100, Peter Maydell wrote: > These have all now been reviewed. Since fw_cfg is marked as > Orphaned in MAINTAINERS, I don't think fw cfg is good as orphaned. Any takers? If not I guess I will have to add myself there. > I'm going to take the series via > target-arm.next. Let me know if anybody would prefer something else. > > thanks > -- PMM Pls go ahead: Reviewed-by: Michael S. Tsirkin > On Fri, 29 May 2026 at 18:46, Peter Maydell wrote: > > > > We support the fw_cfg device on more architectures and machines that > > we let on about in the documentation. Luckily most of the new ones > > (notably riscv and loongarch) have followed the straightforward layout > > that the Arm virt board picked. Allowing every machine type to have > > its own special-snowflake register layout has no particular benefits > > and tends to result in guest OSes accumulating ifdef ladders to deal > > with all the unnecessary variation. > > > > This patchset: > > * updates the docs to present the arm/riscv/loongarch memory > > mapped layout as the "standard" layout to be used by all > > new architectures/machines in future > > * adds the layouts used by various existing boards that we > > didn't document (PA-RISC, SPARC, PPC and MIPS) > > * tightens up fw_cfg_init_mem_dma() and fw_cfg_init_io_dma() > > functions so that they don't provide flexibility to the > > caller to pick their own weird new layout. None of the > > callers were using this flexibility, so it's better to > > have fw_cfg_init_mem_dma() give the "standard MMIO" layout > > and fw_cfg_init_io_dma() give the x86 ioport layout. > > > > thanks > > -- PMM > > > > Peter Maydell (5): > > docs/specs/fw_cfg: Document all architecture register layouts > > hw/nvram/fw_cfg: Enforce standard layout for fw_cfg_init_mem_dma() > > hw/nvram/fw_cfg: Enforce standard layout for x86 fw_cfg I/O ports > > hw/nvram/fw_cfg: Remove support for I/O port fw_cfg without DMA > > hw/nvram/fw_cfg: Document fw_cfg_init_mem_nodma() > > > > docs/specs/fw_cfg.rst | 28 ++++++++++++++++--- > > hw/arm/virt.c | 2 +- > > hw/i386/fw_cfg.c | 3 +- > > hw/i386/microvm.c | 3 +- > > hw/i386/pc.c | 3 +- > > hw/loongarch/fw_cfg.c | 3 +- > > hw/nvram/fw_cfg.c | 22 ++++++--------- > > hw/riscv/virt.c | 3 +- > > include/hw/nvram/fw_cfg.h | 58 +++++++++++++++++++++++++++++++++++---- > > 9 files changed, 92 insertions(+), 33 deletions(-)