Re: [PATCH 04/17] arm64: entry: Add entry-specific helpers

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [Medium] The new exception mask abstraction introduces unnecessary system register reads on exception entry that are immediately discarded, causing overhead on hot paths.
- [Medium] exception_exit_restore_mask() fails to restore PMR and ALLINT, directly contradicting its explicit description in the commit message.

Pre-existing issues:
- [High] Missing pmr_sync() barrier on the PMR unmasking path in local_exception_inherit().
--

commit 2feb968bf7f065e9063df058fc7166adcf349514
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date:   Fri Jul 3 10:01:22 2026 +0000

arm64: entry: Add entry-specific helpers

The existing hacks to bodge pseudo-NMI into the DAIF management code
are convoluted and difficult to maintain. To pave the way for real
hardware NMI support (FEAT_NMI) without compounding the existing
complexity, we need to abstract the low-level exception masking
and unmasking operations into entry-specific helpers.

Link: https://lore.kernel.org/linux-arm-kernel/Y5c9SLeJacLYHmP7@FVFF77S0Q05N/

> diff --git a/arch/arm64/include/asm/exception_masks.h b/arch/arm64/include/asm/exception_masks.h
> index 0a21fb97c3ca8..2c87f7c90f628 100644
> --- a/arch/arm64/include/asm/exception_masks.h
> +++ b/arch/arm64/include/asm/exception_masks.h

[ ... ]

> +static __always_inline struct exception_mask el1_sync_entry_unmask_inherit(struct pt_regs *regs)
> +{
> +	struct exception_mask orig;
> +
> +	local_exception_save_mask(&orig);
> +	local_exception_inherit(regs);

[Severity: High]
This is a pre-existing issue, but does local_exception_inherit() miss a
required pmr_sync() barrier?

When el1_sync_entry_unmask_inherit() calls local_exception_inherit(), it
writes regs->pmr to ICC_PMR_EL1 to unmask interrupts:

	if (system_uses_irq_prio_masking())
		gic_write_pmr(regs->pmr);

Unmasking interrupts via PMR typically requires a pmr_sync() barrier (DSB) so
the priority change is immediately visible to the GIC redistributor. Without
this barrier, the redistributor might delay interrupt delivery.

> +
> +	return orig;
> +}

[ ... ]

> +/*
> + * Mask all exceptions, ready to return to interrupted context
> + */
> +static __always_inline void exception_exit_restore_mask(struct exception_mask mask)
> +{
> +	write_sysreg(mask.daif, daif);
> +}

[Severity: Medium]
Does this function fully match its description in the commit message?

The commit message states that exception_exit_restore_mask() restores both
the DAIF and PMR states:

"- exception_exit_restore_mask(): A unified exit-side helper to safely
   restore the hardware exception mask states (DAIF and PMR)..."
   
However, the implementation only restores DAIF and drops the PMR and ALLINT
states. While kernel_exit and eret might handle those separately in practice,
the documented API contract seems inconsistent with the implementation.

> diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
> index 6fdf74ff48352..dc223085e7735 100644
> --- a/arch/arm64/kernel/entry-common.c
> +++ b/arch/arm64/kernel/entry-common.c

[ ... ]

> @@ -824,7 +849,7 @@ static void noinstr el0_interrupt(struct pt_regs *regs,
>  {
>  	arm64_enter_from_user_mode(regs);
>  
> -	write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
> +	irq_entry_unmask_debug_serror(regs);

[Severity: Medium]
Does discarding the return value of irq_entry_unmask_debug_serror()
introduce unnecessary overhead on the hot EL0 interrupt path?

irq_entry_unmask_debug_serror() calls local_exception_save_mask(), which
executes multiple volatile 'mrs' instructions to read DAIF, PMR, and ALLINT.
Since these reads are performed via asm volatile, the compiler cannot optimize
them out even though the returned exception_mask is ignored here.

>  
>  	if (regs->pc & BIT(55))
>  		arm64_apply_bp_hardening();

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260703100135.2512312-1-ruanjinjie@huawei.com?part=4