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From: sashiko-bot@kernel.org
To: "Sascha Bischoff" <Sascha.Bischoff@arm.com>
Cc: kvm@vger.kernel.org, "Marc Zyngier" <maz@kernel.org>,
	kvmarm@lists.linux.dev, "Oliver Upton" <oupton@kernel.org>
Subject: Re: [PATCH v3 16/40] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI
Date: Fri, 03 Jul 2026 16:35:27 +0000	[thread overview]
Message-ID: <20260703163527.76C871F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260703154811.3355680-17-sascha.bischoff@arm.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Use of `WARN_ON()` wrapping the fallible `irq_set_affinity()` API on a guest-driven WFI path allows a malicious guest to trigger a host denial of service.
- [High] Off-by-one error when computing the Doorbell Priority Mask (DBPM) causes the hardware to miss doorbell signals for valid pending interrupts.
--

commit a810e1cc5f94c1f25b127b180419f6917b92c803
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>
Subject: KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI

This commit adds support for requesting GICv5 VPE doorbells when a vCPU
enters WFI and the VPE becomes non-resident. It sets the doorbell priority
mask to avoid unnecessary wakeups. It also routes the doorbell interrupt to
the current CPU and updates the pending check to observe the doorbell
fired state.

> diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
> index 9c383b6864270..6e976162ec3c2 100644
> --- a/arch/arm64/kvm/vgic/vgic-v5.c
> +++ b/arch/arm64/kvm/vgic/vgic-v5.c
> @@ -1094,6 +1094,46 @@ void vgic_v5_put(struct kvm_vcpu *vcpu)
>  	kvm_call_hyp(__vgic_v5_save_apr, cpu_if);
>  
>  	cpu_if->vgic_contextr = 0;
> +	if (vcpu_get_flag(vcpu, IN_WFI)) {
> +		u32 priority_mask;
> +		int dbpm;
> +
> +		/*
> +		 * Find the virtual running priority and use this to calculate
> +		 * the doorbell priority mask. We combine the highest active
> +		 * priority and the CPU's priority mask. The guest can't handle
> +		 * interrupts with priorities less than or equal to the virtual
> +		 * running priority, so there's literally no point in waking the
> +		 * guest for these.
> +		 *
> +		 * The priority needs to be higher than the mask to signal, so
> +		 * pick the next higher priority (subtract 1).
> +		 */
> +		priority_mask = vgic_v5_get_effective_priority_mask(vcpu);
> +
> +		/*
> +		 * Request a doorbell *unless* the priority is 0, indicating
> +		 * that no interrupt can wake the CPU up.
> +		 */
> +		if (priority_mask) {
> +			int db_irq = vgic_v5_vpe_db(vcpu);
> +			struct irq_data *d = irq_get_irq_data(db_irq);
> +			const struct cpumask *aff = irq_data_get_effective_affinity_mask(d);
> +			int cpu = smp_processor_id();
> +
> +			dbpm = priority_mask - 1;
> +			cpu_if->vgic_contextr = FIELD_PREP(ICH_CONTEXTR_EL2_DB, 1) |
> +						FIELD_PREP(ICH_CONTEXTR_EL2_DBPM, dbpm);

[Severity: High]
Does this subtraction configure the mask too strictly? Since the hardware
already evaluates using a strictly-less-than check (Priority < DBPM), would
setting it to priority_mask - 1 cause the hardware to miss doorbell signals
for interrupts arriving at the lowest unmasked priority level?

> +
> +			/*
> +			 * Make the doorbell affine to this CPU, if it isn't
> +			 * already. Actively check the cpumask first as it is
> +			 * cheaper than changing the affinity every time.
> +			 */
> +			if (!cpumask_test_cpu(cpu, aff))
> +				WARN_ON(irq_set_affinity(db_irq, cpumask_of(cpu)));

[Severity: High]
Should we handle the failure of irq_set_affinity() here without using a
WARN_ON()?

Because this is a fallible API and the WFI path is driven directly by the
guest, a malicious guest could execute WFI in a tight loop to trigger this
warning continuously. This could lead to a host denial of service either
through severe log spam or a panic if panic_on_warn is enabled.

> +		}
> +	}
>  
>  	kvm_call_hyp(__vgic_v5_make_non_resident, cpu_if);
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260703154811.3355680-1-sascha.bischoff@arm.com?part=16

  reply	other threads:[~2026-07-03 16:35 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-03 15:50 [PATCH v3 00/40] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-07-03 15:51 ` [PATCH v3 01/40] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-07-03 16:33   ` sashiko-bot
2026-07-07 12:30     ` Sascha Bischoff
2026-07-03 15:51 ` [PATCH v3 02/40] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-07-03 16:24   ` sashiko-bot
2026-07-07 12:48     ` Sascha Bischoff
2026-07-03 15:52 ` [PATCH v3 03/40] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-07-03 15:52 ` [PATCH v3 04/40] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-07-03 15:53 ` [PATCH v3 05/40] arm64/sysreg: Add GICv5 GIC VDPEND and VDRCFG encodings Sascha Bischoff
2026-07-03 16:28   ` sashiko-bot
2026-07-07 14:28     ` Sascha Bischoff
2026-07-03 15:53 ` [PATCH v3 06/40] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-07-03 16:22   ` sashiko-bot
2026-07-07 15:08     ` Sascha Bischoff
2026-07-03 15:54 ` [PATCH v3 07/40] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-07-03 15:54 ` [PATCH v3 08/40] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-07-03 16:25   ` sashiko-bot
2026-07-07 15:11     ` Sascha Bischoff
2026-07-03 15:55 ` [PATCH v3 09/40] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-07-03 16:31   ` sashiko-bot
2026-07-08 14:44     ` Sascha Bischoff
2026-07-03 15:55 ` [PATCH v3 10/40] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-07-03 16:34   ` sashiko-bot
2026-07-08 14:46     ` Sascha Bischoff
2026-07-03 15:56 ` [PATCH v3 11/40] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-07-03 16:39   ` sashiko-bot
2026-07-08 14:49     ` Sascha Bischoff
2026-07-03 15:56 ` [PATCH v3 12/40] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-07-03 15:57 ` [PATCH v3 13/40] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-07-03 16:26   ` sashiko-bot
2026-07-08 14:53     ` Sascha Bischoff
2026-07-03 15:57 ` [PATCH v3 14/40] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-07-03 16:27   ` sashiko-bot
2026-07-08 14:56     ` Sascha Bischoff
2026-07-03 15:58 ` [PATCH v3 15/40] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-07-03 16:23   ` sashiko-bot
2026-07-08 15:00     ` Sascha Bischoff
2026-07-03 15:58 ` [PATCH v3 16/40] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-07-03 16:35   ` sashiko-bot [this message]
2026-07-08 15:35     ` Sascha Bischoff
2026-07-03 15:59 ` [PATCH v3 17/40] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-07-03 15:59 ` [PATCH v3 18/40] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-07-03 16:00 ` [PATCH v3 19/40] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-07-03 16:00 ` [PATCH v3 20/40] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-07-03 16:38   ` sashiko-bot
2026-07-09  9:28     ` Sascha Bischoff
2026-07-03 16:01 ` [PATCH v3 21/40] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-07-03 16:01 ` [PATCH v3 22/40] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-07-03 16:47   ` sashiko-bot
2026-07-09  9:55     ` Sascha Bischoff
2026-07-03 16:02 ` [PATCH v3 23/40] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-07-03 16:34   ` sashiko-bot
2026-07-09 11:39     ` Sascha Bischoff
2026-07-03 16:02 ` [PATCH v3 24/40] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-07-03 16:03 ` [PATCH v3 25/40] KVM: arm64: gic-v5: Introduce SPI AP list Sascha Bischoff
2026-07-03 16:03 ` [PATCH v3 26/40] KVM: arm64: gic-v5: Add GIC VDPEND and GIC VDRCFG hyp calls Sascha Bischoff
2026-07-03 16:31   ` sashiko-bot
2026-07-10  9:44     ` Sascha Bischoff
2026-07-03 16:04 ` [PATCH v3 27/40] KVM: arm64: gic-v5: Track SPI state for in-flight SPIs Sascha Bischoff
2026-07-03 16:41   ` sashiko-bot
2026-07-03 16:04 ` [PATCH v3 28/40] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-07-03 16:32   ` sashiko-bot
2026-07-10  9:51     ` Sascha Bischoff
2026-07-03 16:05 ` [PATCH v3 29/40] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-07-03 16:53   ` sashiko-bot
2026-07-03 16:05 ` [PATCH v3 30/40] Documentation: KVM: Extend VGICv5 docs for KVM_VGIC_V5_ADDR_TYPE_IRS Sascha Bischoff
2026-07-03 16:27   ` sashiko-bot
2026-07-03 16:06 ` [PATCH v3 31/40] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-07-03 16:36   ` sashiko-bot
2026-07-03 16:06 ` [PATCH v3 32/40] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-07-03 16:07 ` [PATCH v3 33/40] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-07-03 16:07 ` [PATCH v3 34/40] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-07-03 16:42   ` sashiko-bot
2026-07-03 16:08 ` [PATCH v3 35/40] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-07-03 16:41   ` sashiko-bot
2026-07-03 16:08 ` [PATCH v3 36/40] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-07-03 16:43   ` sashiko-bot
2026-07-03 16:09 ` [PATCH v3 37/40] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-07-03 16:36   ` sashiko-bot
2026-07-03 16:09 ` [PATCH v3 38/40] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-07-03 16:37   ` sashiko-bot
2026-07-03 16:10 ` [PATCH v3 39/40] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-07-03 16:10 ` [PATCH v3 40/40] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-07-03 16:33   ` sashiko-bot

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