[PATCH 2/4] target/hppa: Delay MMU update until TLB protection bits were set

[Helge Deller <deller@kernel.org>]

From: Helge Deller <deller@gmx.de>

On a 32-bit HPPA CPU, the TLB update for a data translation happens with
two consecutive instructions: IDTLBA and IDTLBP. The former sets the
target page address, while the second sets the protection bits.
There is no need to update the MMU after setting the address bits only,
so delay the final update of the MMU until after the execution of the
second instruction when the protection bits are known too.

Signed-off-by: Helge Deller <deller@gmx.de>
---
 target/hppa/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4e34822565..002189ddfb 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2570,7 +2570,7 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
     }
 
     /* Exit TB for TLB change if mmu is enabled.  */
-    if (ctx->tb_flags & PSW_C) {
+    if (ctx->tb_flags & PSW_C && !a->addr) {
         ctx->base.is_jmp = DISAS_IAQ_N_STALE;
     }
     return nullify_end(ctx);
@@ -2687,7 +2687,7 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
     }
 
     /* Exit TB for TLB change if mmu is enabled.  */
-    if (ctx->tb_flags & PSW_C) {
+    if (ctx->tb_flags & PSW_C && !a->addr) {
         ctx->base.is_jmp = DISAS_IAQ_N_STALE;
     }
     return nullify_end(ctx);
-- 
2.54.0