From: sashiko-bot@kernel.org
To: "Anna Maniscalco" <anna.maniscalco2000@gmail.com>
Cc: dri-devel@lists.freedesktop.org, robh@kernel.org,
devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH RFC 10/13] drm/msm: initialize LPAC ring
Date: Sun, 05 Jul 2026 19:26:30 +0000 [thread overview]
Message-ID: <20260705192631.1BE491F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260705-descriptive-name-lpac-upstream-v1-10-01d50c3e0c99@gmail.com>
Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [Critical] Unconditional execution of LPAC initialization on all A6xx/A7xx GPUs will crash hardware without LPAC support.
- [High] The error check for the LPAC ringbuffer allocation evaluates the wrong variable, ignoring allocation failures and reading out-of-bounds.
- [Medium] The GPU hangcheck timer does not monitor the LPAC ring, causing LPAC-only hangs to go undetected.
- [Medium] Missing cleanup of `gpu->lpac_rb` in the error path of `msm_gpu_init()`.
- [Low] Unconditional allocation of the LPAC ringbuffer wastes resources for all MSM GPUs.
--
commit 35c6bd5d02bb9ed8858bdd2395719b06651d77e8
Author: Anna Maniscalco <anna.maniscalco2000@gmail.com>
drm/msm: initialize LPAC ring
Program all the register needed to start up LPAC and send initialization
sequence. Additionally, now that the LPAC ring is live, make the code aware
of it.
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
[ ... ]
> @@ -1481,6 +1567,10 @@ static int hw_init(struct msm_gpu *gpu)
> if (ret)
> goto out;
>
> + ret = lpac_cp_init(gpu);
> + if (ret)
> + goto out;
> +
[Severity: Critical]
Will this unconditional execution of LPAC initialization cause a regression on
hardware without LPAC support?
During hw_init(), the driver unconditionally writes to LPAC-specific registers
and calls lpac_cp_init(). This function sends a CP_ME_INIT packet to the LPAC
ring and waits for it to idle using a6xx_idle().
On older GPUs lacking LPAC hardware (e.g., A630), the CP engine ignores this
ring, causing the idle wait to time out and hw_init() to return -EINVAL.
> /*
> * Try to load a zap shader into the secure world. If successful
[ ... ]
> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
> --- a/drivers/gpu/drm/msm/msm_gpu.c
> +++ b/drivers/gpu/drm/msm/msm_gpu.c
[ ... ]
> @@ -1006,6 +1009,15 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> memptrs_iova += sizeof(struct msm_rbmemptrs);
> }
>
> + gpu->lpac_rb = msm_ringbuffer_new(gpu, nr_rings, memptrs, memptrs_iova);
> +
[Severity: Low]
Does this unconditional allocation of the LPAC ringbuffer waste resources for
legacy non-LPAC GPUs?
A GEM object, DRM scheduler kthread, and fence context are allocated for every
MSM GPU even if they do not support LPAC.
> + if (IS_ERR(gpu->rb[i])) {
> + ret = PTR_ERR(gpu->rb[i]);
> + DRM_DEV_ERROR(drm->dev,
> + "could not create lpac ringbuffer %d\n", ret);
> + goto fail;
> + }
> +
[Severity: High]
Does this check the wrong variable for the LPAC allocation failure?
The error check evaluates gpu->rb[i] instead of gpu->lpac_rb. If the LPAC
allocation fails, gpu->lpac_rb holds an error pointer but the initialization
succeeds.
This later causes a kernel panic when the error pointer is dereferenced during
device setup. Additionally, because the loop counter i equals nr_rings here,
checking gpu->rb[i] results in an out-of-bounds array read if nr_rings equals
MSM_GPU_MAX_RINGS.
[Severity: Medium]
If GPU initialization fails and we take this goto fail path, is there a memory
leak for the LPAC ringbuffer?
The fail path in msm_gpu_init() iterates over gpu->rb and destroys those
ringbuffers, but it lacks a call to msm_ringbuffer_destroy(gpu->lpac_rb).
> gpu->nr_rings = nr_rings;
>
> refcount_set(&gpu->sysprof_active, 1);
[ ... ]
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
[ ... ]
> @@ -181,6 +181,8 @@ struct msm_gpu {
> struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
> int nr_rings;
>
> + struct msm_ringbuffer *lpac_rb;
> +
[Severity: Medium]
Is the GPU hangcheck timer missing monitoring for the LPAC ring?
In msm_gpu.c:hangcheck_handler(), the code only monitors the primary active
ring:
struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
...
if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence))
hangcheck_timer_reset(gpu);
If a task submitted to the LPAC ring hangs and the primary ring is idle,
fence_after() evaluates to false and the timer is not reset. The stall goes
undetected, leaving the task hanging indefinitely without GPU recovery.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260705-descriptive-name-lpac-upstream-v1-0-01d50c3e0c99@gmail.com?part=10
next prev parent reply other threads:[~2026-07-05 19:26 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-05 19:13 [RFC PATCH 00/13] Enable LPAC on a7xx series GPUs Anna Maniscalco
2026-07-05 19:13 ` [PATCH RFC 01/13] iommu: arm-smmu-qcom: Configure lpac device with split address space Anna Maniscalco
2026-07-06 15:00 ` Dmitry Baryshkov
2026-07-07 15:04 ` Anna Maniscalco
2026-07-05 19:13 ` [PATCH RFC 02/13] drm/msm: add support for lpac_domain in msm_mmu Anna Maniscalco
2026-07-05 19:27 ` sashiko-bot
2026-07-05 19:13 ` [PATCH RFC 03/13] drm/msm: look for lpac from dts Anna Maniscalco
2026-07-05 19:27 ` sashiko-bot
2026-07-06 15:04 ` Dmitry Baryshkov
2026-07-07 15:02 ` Anna Maniscalco
2026-07-07 16:39 ` Dmitry Baryshkov
2026-07-09 13:42 ` Akhil P Oommen
2026-07-09 14:54 ` Dmitry Baryshkov
2026-07-09 19:39 ` Dmitry Baryshkov
2026-07-05 19:13 ` [PATCH RFC 04/13] arm64: dts: qcom: sm8650: move smmu sid 1 to new lpac device Anna Maniscalco
2026-07-05 19:24 ` sashiko-bot
2026-07-06 8:40 ` Konrad Dybcio
2026-07-05 19:13 ` [PATCH RFC 05/13] firmware: qcom: scm: Configure LPAC aperture Anna Maniscalco
2026-07-05 19:20 ` sashiko-bot
2026-07-05 19:13 ` [PATCH RFC 06/13] DEBUGGING: print contextbank and other ttbrs on fault Anna Maniscalco
2026-07-05 19:13 ` [PATCH RFC 07/13] iommu: arm-smmu-qcom: Fixed mapping between sid and cb for gpu and lpac Anna Maniscalco
2026-07-05 19:27 ` sashiko-bot
2026-07-05 19:13 ` [PATCH RFC 08/13] HACK: use cb1 address in lpac dtb node Anna Maniscalco
2026-07-05 19:18 ` sashiko-bot
2026-07-05 19:13 ` [PATCH RFC 09/13] temp: add LPAC regs Anna Maniscalco
2026-07-05 19:23 ` sashiko-bot
2026-07-05 19:13 ` [PATCH RFC 10/13] drm/msm: initialize LPAC ring Anna Maniscalco
2026-07-05 19:26 ` sashiko-bot [this message]
2026-07-06 8:44 ` Konrad Dybcio
2026-07-06 11:07 ` Anna Maniscalco
2026-07-06 11:09 ` Konrad Dybcio
2026-07-06 21:56 ` Akhil P Oommen
2026-07-06 22:13 ` Anna Maniscalco
2026-07-05 19:13 ` [PATCH RFC 11/13] drm/msm: Add LPAC submitqueue Anna Maniscalco
2026-07-05 19:36 ` sashiko-bot
2026-07-05 19:13 ` [PATCH RFC 12/13] drm/msm: set ctxbank and asid based on ring Anna Maniscalco
2026-07-05 19:13 ` [PATCH RFC 13/13] drm/msm: add lpac ring to devcoredump Anna Maniscalco
2026-07-05 19:35 ` sashiko-bot
2026-07-06 14:57 ` [RFC PATCH 00/13] Enable LPAC on a7xx series GPUs Dmitry Baryshkov
2026-07-06 22:00 ` Akhil P Oommen
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